TY - CHAP A1 - Andjelkovic, Marko A1 - Ilic, Aleksandar A1 - Stamenković, Zoran A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - An Overview of the Current Models for the Circuit-level Simulations of Single Event Transients T2 - Book of abstracts, 5th International Conference on Radiation and Applications in Various Fields of Research (RAD 2017), June 12-16, 2017, Budva, Montenegro Y1 - 2017 SP - S. 184 ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Ilic, Aleksandar A1 - Stamenković, Zoran A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - An Overview of the Modeling and Simulation of the Single Event Transients at the Circuit Level T2 - 30th International Conference on Microelectronics (MIEL), 9-11 Oct. 2017, Nis, Serbia Y1 - 2017 SN - 978-1-5386-2563-7 SN - 978-1-5386-2561-3 U6 - https://doi.org/10.1109/MIEL.2017.8190065 SP - 35 EP - 44 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Assessment of the Amplitude-duration Criterion for SET Robusness Evaluation T2 - 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, Greece, 3-5 July 2017 Y1 - 2017 SN - 978-1-5386-0352-9 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Simevski, Aleksandar A1 - Schleisiek, Klaus A1 - Petrovic, Vladimir A1 - Beller, Norbert A1 - Skoncej, Patryk A1 - Schoof, Gunther A1 - Krstic, Milos T1 - Implementation of a Real Time Unit for Satellite Applications T2 - 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 20-22 April 2016, Kosice, Slovakia Y1 - 2016 SN - 978-1-5090-2467-4 SP - 180 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Krstic, Milos A1 - Fan, Xin A1 - Babic, Milan A1 - Grass, Eckhard A1 - Bjerregaard, T. A1 - Yakovlev, A. T1 - Reducing Switching Noise Effects by Advanced Clock Management T2 - 11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo), 4-8 July, St. Petersburg, Russia 2017 Y1 - 2017 SN - 978-1-5386-2689-4 SP - 3 EP - 8 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Zeidler, Steffen A1 - Krstic, Milos T1 - GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits T2 - 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2016), 8-11 May, Porto Alegre, Brazil, 2016 Y1 - 2016 SN - 978-1-4673-9007-1 SP - 67 EP - 74 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Petrovic, Vladimir A1 - Nenadovic, Miljana A1 - Breitenreiter, Anselm A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Design of an On-Chip System for the SET Pulse Width Measurement T2 - Euromicro Conference on Digital System Design, 30 Aug.-1 Sept., Vienna, Austria 2017 Y1 - 2017 SN - 978-1-5386-2146-2 SP - 111 EP - 118 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf A1 - Veeravalli, Varadan Savulimedu A1 - Steininger, Andreas T1 - Erstellung eines Modells der kritischen Ladung zur Bewertung der Robustheit gegenüber SETs und SEUs: Fallstudie Muller C-Element T2 - Zuverlässigkeit und Entwurf, 9. ITG/GMM/GI-Fachtagung vom 18.-20. September 2017 in Cottbus Y1 - 2017 SN - 978-3-8007-4444-2 SP - 17 EP - 24 PB - Berlin CY - VDE Verlag ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Nenadovic, Miljana A1 - Petrovic, Vladimir A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Evaluation of the Pulse Stretcher for Detection of Very Short Single Event Transients T2 - Book of abstracts, 5th International Conference on Radiation and Applications in Various Fields of Research (RAD 2017), Budva, Montenegro, 2017 Y1 - 2017 UR - http://rad2017.rad-conference.org/news.php SP - S. 214 ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Comparison of the SET Sensitivity of Standard Logic Gates Designed in 130 nm CMOS Technology T2 - 30th International Conference on Microelectronics (MIEL), 9-11 Oct. 2017, Nis, Serbia Y1 - 2017 SN - 978-1-5386-2563-7 SN - 978-1-5386-2561-3 U6 - https://doi.org/10.1109/MIEL.2017.8190106 SP - 217 EP - 220 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Jagdhold, Ulrich A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - 2D TCAD Simulation of Single Event Transients in 250 nm Bulk CMOS Technology T2 - Zuverlässigkeit und Entwurf, 9. ITG/GMM/GI-Fachtagung vom 18.-20. September 2017 in Cottbus Y1 - 2017 SN - 978-3-8007-4444-2 SP - 90 EP - 96 PB - Berlin CY - VDE Verlag ER - TY - CHAP A1 - Babic, Milan A1 - Krstic, Milos T1 - A Substrate Noise Reduction Methodology Based on Power Domain Separation of GALS Subcomponents T2 - 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), September 25-27, 2017, Aristotle University Research Dissemination Center (KEDEA), Thessaloniki, Greece Y1 - 2017 SN - 978-1-5090-6462-5 U6 - https://doi.org/10.1109/PATMOS.2017.8106981 SP - 6 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Krstic, Milos T1 - GALS Methodology for Substrate Noise Reduction in BiCMOS Technologies T2 - Proceedings, Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN), Tallinn, Estonia, 2015 Y1 - 2015 UR - http://www.median-project.eu/wp-content/uploads/MEDIAN-Finale-s2-3.pdf ER - TY - CHAP A1 - Babic, Milan A1 - Krstic, Milos T1 - A Coarse Model for Estimation of Switching Noise Coupling in Lightly Doped Substrates T2 - 18th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Belgrade, Serbia, 2015 Y1 - 2015 SN - 978-1-4799-6780-3 SN - 978-1-4799-6779-7 SP - 217 EP - 222 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Babic, Milan A1 - Fan, Xin A1 - Krstic, Milos T1 - Frequency-Domain Modeling of Ground Bounce and Substrate Noise for Synchronous and GALS Systems T2 - 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 1-4 Sept. Salvador, Brazil 2015 Y1 - 2015 SN - 978-1-4673-9419-2 SP - 126 EP - 132 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf A1 - Veeravalli, Varadan Savulimedu A1 - Steininger, Andreas T1 - A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study T2 - IEEE 26th Asian Test Symposium (ATS), Taipei, Taiwan, 28-30 November 2017 Y1 - 2017 SN - 978-1-5386-2437-1 U6 - https://doi.org/10.1109/ATS.2017.27 SP - 78 EP - 83 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Stamenković, Zoran A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Impact of Resistive Open and Bridge Defects on the SET Robustness of CMOS Combinational Logic T2 - IEEE East-West Design & Test Symposium (EWDTS 2018), Kazan, Russia, 14 - 17 September 2018 Y1 - 2018 SN - 978-1-5386-5709-6 U6 - https://doi.org/10.1109/EWDTS.2018.8524748 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Andjelkovic, Marko A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Study of the Operation and SET Robustness of a CMOS Pulse Stretching Circuit T2 - Microelectronics Reliability Y1 - 2018 U6 - https://doi.org/10.1016/j.microrel.2017.12.022 SN - 0026-2714 SN - 1872-941X VL - 82 SP - 100 EP - 112 ER - TY - CHAP A1 - Andjelkovic, Marko A1 - Babic, Milan A1 - Li, Yuanqing A1 - Schrape, Oliver A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational Gates T2 - 25th IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), Bordeaux, France, 09 - 12 December 2018 Y1 - 2018 SN - 978-1-5386-9562-3 SN - 978-1-5386-9116-8 U6 - https://doi.org/10.1109/ICECS.2018.8617996 SP - 361 EP - 364 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Segabinazzi Ferreira, Raphael A1 - George, Nevin A1 - Chen, Junchao A1 - Hübner, Michael A1 - Krstic, Milos A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor T1 - Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness T2 - Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design N2 - Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on- line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system. Y1 - 2019 SN - 978-3-902457-54-7 U6 - https://doi.org/10.26127/BTUOpen-5050 PB - SEA-Publications CY - Kallithea, Chalkidiki (Greece) ER - TY - GEN A1 - Andjelkovic, Marko A1 - Li, Yuanqing A1 - Stamenković, Zoran A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Characterization and Modeling of SET Generation Effects in CMOS Standard Logic Cells T2 - 25th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2019), Rhodos, Greece, 01 - 03 July 2019 Y1 - 2019 SN - 978-1-7281-2490-2 SN - 978-1-7281-2489-6 SN - 978-1-7281-2491-9 U6 - https://doi.org/10.1109/IOLTS.2019.8854379 SN - 1942-9401 PB - IEEE ER - TY - GEN A1 - Veleski, Mitko A1 - Kraemer, Rolf A1 - Krstic, Milos T1 - SWIELD: An In Situ Approach for Adaptive Low Power and Error-Resilient Operation T2 - 17th IEEE East-West Design & Test Symposium (EWDTS 2019), Batumi, Georgia, 13 - 16 September 2019 Y1 - 2019 SN - 978-1-7281-1003-5 SN - 978-1-7281-1002-8 SN - 978-1-7281-1004-2 U6 - https://doi.org/10.1109/EWDTS.2019.8884428 SN - 2472-761X PB - IEEE ER -