TY - CHAP A1 - Lopacinski, Lukasz A1 - Brzozowski, Marcin A1 - Kraemer, Rolf A1 - KrishneGowda, Karthik A1 - Büchner, Steffen A1 - Nolte, Jörg T1 - Towards 100 Gbps Wireless Communication: Investigation of FEC Interleavers for PSSS-15 Spreading T2 - IEEE EUROCON 2017, 17th International Conference on Smart Technologies, Ohrid, Macedonia, 6-8 July 2017 Y1 - 2017 SN - 978-1-5090-3843-5 SP - 619 EP - 623 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Scheytt, J. Christoph A1 - Rehman Javed, Abdul A1 - Bammidi, Eswara Rao A1 - KrishneGowda, Karthik A1 - Kallfass, Ingmar A1 - Kraemer, Rolf T1 - 100 Gbps Wireless System and Circuit Design Using Parallel Spread-Spectrum Sequencing T2 - Frequenz: Journal of RF-Engineering and Telecommunications Y1 - 2017 SN - 0016-1136 SN - 2191-6349 VL - 71 IS - 9-10 SP - 399 EP - 414 ER - TY - CHAP A1 - Rehman Javed, Abdul A1 - KrishneGowda, Karthik A1 - Scheytt, J. Christoph A1 - Kraemer, Rolf T1 - System Design Considerations for a PSSS Transceiver for 100 Gbps Wireless Communication with Emphasis on Mixed Signal Implementation T2 - 16th Annual Wireless and Microwave Technology Conference (WAMICON), Cocoa Beach, USA, 2015 Y1 - 2015 SN - 978-1-4799-7521-1 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - KrishneGowda, Karthik A1 - Messinger, Tobias A1 - Wolf, Andreas C. A1 - Kraemer, Rolf A1 - Kallfass, Ingmar A1 - Scheytt, J. Christoph T1 - Towards 100 Gbps Wireless Communication in THz Band with PSSS Modulation: A Promising Hardware in the Loop Experiment T2 - IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB), 4-7 Oct. 2015 Montreal, Canada, 2015 Y1 - 2015 SN - 978-1-4673-6555-0 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Messinger, Tobias A1 - KrishneGowda, Karthik A1 - Boes, Florian A1 - Meier, Dominik A1 - Wolf, Andreas C. A1 - Tessmann, Axel A1 - Kraemer, Rolf A1 - Kallfass, Ingmar T1 - Multi-Level 20 Gbit/s PSSS Transmission Using a Linearity-Limited 240 GHz Wireless Frontend T2 - International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS), Tel-Aviv, Israel, 2-4 Nov. 2015 Y1 - 2015 SN - 978-1-4799-7473-3 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Perez, Eduardo A1 - Uhlmann, Max A1 - Fritscher, Markus A1 - KrishneGowda, Karthik A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator T2 - 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) N2 - The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 % and 18 %, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero. KW - RRAM Y1 - 2024 SN - 978-3-9819263-8-5 SN - 979-8-3503-4860-6 U6 - https://doi.org/10.23919/DATE58400.2024.10546709 SN - 1558-1101 SP - 1 EP - 6 PB - IEEE ER -