TY - GEN A1 - Dziallas, Giannino A1 - Fatemi, Adel A1 - Korndörfer, Falk A1 - Peczek, Anna A1 - Kissinger, Dietmar A1 - Zimmermann, Lars A1 - Malignaggi, Andrea A1 - Kahmen, Gerhard T1 - A Monolithically Integrated Optical Bandpass Receiver in 0.25μm SiGe BiCMOS Technology for Microwave-Photonic Applications T2 - 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), November 9-11, 2020 ONLINE Y1 - 2020 SN - 978-1-7281-8436-4 SN - 978-1-7281-8437-1 U6 - https://doi.org/10.1109/A-SSCC48613.2020.9336119 ER - TY - GEN A1 - Fritscher, Markus A1 - Singh, Simranjeet A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Reiser, Daniel A1 - Mallah, Maen A1 - Hartmann, David A1 - Bende, Ankit A1 - Kempen, Tim A1 - Uhlmann, Max A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Rana, Vikas A1 - Menzel, Stephan A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Merchant, Farhad A1 - Wenger, Christian T1 - A flexible and fast digital twin for RRAM systems applied for training resilient neural networks T2 - Scientific Reports N2 - Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT). KW - RRAM KW - Neural network KW - digital twin Y1 - 2024 U6 - https://doi.org/10.1038/s41598-024-73439-z SN - 2045-2322 VL - 14 IS - 1 PB - Springer Science and Business Media LLC ER - TY - GEN A1 - Fritscher, Markus A1 - Uhlmann, Max A1 - Ostrovskyy, Philip A1 - Reiser, Daniel A1 - Chen, Junchao A1 - Schubert, Andreas A1 - Schulze, Carsten A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Wenger, Christian T1 - Area-efficient digital design using RRAM-CMOS standard cells T2 - 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) N2 - Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 % smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 %. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core. KW - RRAM Y1 - 2024 SN - 979-8-3503-5411-9 SN - 979-8-3503-5412-6 U6 - https://doi.org/10.1109/ISVLSI61997.2024.00026 SN - 2159-3477 VL - 18 SP - 81 EP - 87 PB - IEEE ER - TY - GEN A1 - Uhlmann, Max A1 - Rizzi, Tommaso A1 - Wen, Jianan A1 - Pérez-Bosch Quesada, Emilio A1 - Al Beattie, Bakr A1 - Ochs, Karlheinz A1 - Pérez, Eduardo A1 - Ostrovskyy, Philip A1 - Carta, Corrado A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - LUT-based RRAM model for neural accelerator circuit simulation T2 - Proceedings of the 18th ACM International Symposium on Nanoscale Architectures N2 - Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices’ models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP’s 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis. KW - RRAM KW - Neural network Y1 - 2023 U6 - https://doi.org/10.1145/3611315.3633273 SP - 1 EP - 6 PB - ACM CY - New York, NY, USA ER - TY - GEN A1 - Kahmen, Gerhard T1 - SiGe BiCMOS as Enabling Technology for Next Generation RF & THz Systems T2 - EuMIC 2021 Abstract Cards, 16th European Microwave Integrated Circuits Conference (EuMIC), London, United Kingdom, 2022 Y1 - 2022 U6 - https://doi.org/10.23919/EuMIC50153.2022.9783893 SP - S. 21 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Sütbas, Batuhan A1 - Ng, Herman Jalli A1 - Wessel, Jan A1 - Kölpin, Alexander A1 - Kahmen, Gerhard T1 - A V-band Low-Power and Compact Down-Conversion Mixer with Low LO Power in 130-nm SiGe BiCMOS Technology T2 - 16th European Microwave Integrated Circuits Conference (EuMIC), 03-04 April 2022, London, United Kingdom Y1 - 2022 U6 - https://doi.org/10.23919/EuMIC50153.2022.9783953 ER - TY - GEN A1 - Sütbas, Batuhan A1 - Ngy, Herman Jalli A1 - Wessel, Jan A1 - Kölpin, Alexander A1 - Kahmen, Gerhard T1 - Low-Power Ka- and V-Band Miller Compensated Amplifiers in 130-nm SiGe BiCMOS Technology T2 - 16th European Microwave Integrated Circuits Conference (EuMIC), 03-04 April 2022, London, United Kingdom Y1 - 2022 SN - 978-2-87487-064-4 SN - 978-1-6654-4722-5 U6 - https://doi.org/10.23919/EuMIC50153.2022.9783785 ER - TY - GEN A1 - Sütbas, Batuhan A1 - Kahmen, Gerhard T1 - A 7.2-mW V-Band Frequency Doubler with 14% Total Efficiency in 130-nm SiGe BiCMOS T2 - IEEE Microwave and Wireless Components Letters Y1 - 2022 U6 - https://doi.org/10.1109/LMWC.2022.3141557 SN - 1531-1309 SN - 1558-1764 VL - 32 IS - 6 SP - 579 EP - 582 ER - TY - GEN A1 - Dziallas, Giannino A1 - Fatemi, Adel A1 - Peczek, Anna A1 - Zimmermann, Lars A1 - Malignaggi, Andrea A1 - Kahmen, Gerhard T1 - A 56-Gb/s Optical Receiver with 2.08-µA Noise Monolithically Integrated into a 250-nm SiGe BiCMOS Technology T2 - IEEE Transactions on Microwave Theory and Techniques Y1 - 2022 U6 - https://doi.org/10.1109/TMTT.2021.3104838 SN - 0018-9480 SN - 1557-9670 VL - 70 IS - 1 ER - TY - GEN A1 - Eissa, Mohamed Hussein A1 - Fischer, Gunter A1 - Mausolf, Thomas A1 - Rücker, Holger A1 - Malignaggi, Andrea A1 - Kahmen, Gerhard T1 - 220-320-GHz J-Band 4-Way Power Amplifier in Advanced 130-nm BiCMOS Technology T2 - IEEE Microwave and Wireless Components Letters Y1 - 2022 U6 - https://doi.org/10.1109/LMWC.2022.3181407 SN - 1531-1309 SN - 1558-1764 VL - 32 IS - 11 SP - 1335 EP - 1338 ER - TY - GEN A1 - Iseini, Festim A1 - Malignaggi, Andrea A1 - Korndörfer, Falk A1 - Inac, Mesut A1 - Kahmen, Gerhard T1 - Lumped Ultra-Broadband Linear Driver in 130 nm SiGe SG13G3 Technology T2 - IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) Y1 - 2022 U6 - https://doi.org/10.1109/BCICTS53451.2022.10051703 ER - TY - GEN A1 - Uhlmann, Max A1 - Pérez-Bosch Quesada, Emilio A1 - Fritscher, Markus A1 - Pérez, Eduardo A1 - Schubert, Markus Andreas A1 - Reichenbach, Marc A1 - Ostrovskyy, Philip A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS) N2 - The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications. KW - RRAM KW - In-Memory Computing Y1 - 2023 SN - 979-8-3503-0024-6 SN - 979-8-3503-0025-3 U6 - https://doi.org/10.1109/NEWCAS57931.2023.10198073 SN - 2474-9672 SN - 2472-467X PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Iseini, Festim A1 - Lin, Han-Ting A1 - Pelagalli, Nicola A1 - Malinaggi, Andrea A1 - Carta, Corrado A1 - Kahmen, Gerhard A1 - Weisshaar, Andreas T1 - A tunable inductor peaking technique for optical communication systems T2 - 2024 IEEE 33rd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Toronto, ON, Canada, 2024 N2 - A tunable inductor peaking technique for loss compensation in optical communication systems is presented. The proposed technique is based on creating a tunable damped resonator with a fixed peaking inductor and a high-frequency transistor with low intrinsic capacitance. The tuning technique is first demonstrated with a generic equivalent circuit model and then implemented and evaluated using the high-speed bipolar transistor in 130 nm IHP SG13G2 BiCMOS technology, featuring ft/fmax of 350 / 450 GHz. Our proposed technique has been simulated in a real case scenario demonstrating the effectiveness of the tunable inductor peaking technique for loss compensation in optical communication systems. Y1 - 2024 UR - https://ieeexplore.ieee.org/document/10753708 SN - 979-8-3503-5123-1 U6 - https://doi.org/10.1109/EPEPS61853.2024.10753708 SP - 1 EP - 3 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER - TY - GEN A1 - Fritscher, Markus A1 - Uhlmann, Max A1 - Ostrovskyy, Philip A1 - Reiser, Daniel A1 - Chen, Junchao A1 - Wen, Jianan A1 - Schulze, Carsten A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Wenger, Christian ED - Wenger, Christian T1 - RISC-V CPU design using RRAM-CMOS standard cells T2 - IEEE transactions on very large scale integration (VLSI) systems N2 - The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates. KW - RRAM KW - Logic gates Y1 - 2025 UR - https://ieeexplore.ieee.org/document/10960690 U6 - https://doi.org/10.1109/TVLSI.2025.3554476 SN - 1063-8210 SP - 1 EP - 9 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER - TY - GEN A1 - Uhlmann, Max A1 - Krysik, Milosz A1 - Wen, Jianan A1 - Frohberg, Max A1 - Baroni, Andrea A1 - Reddy, Keerthi Dorai Swamy A1 - Pérez, Eduardo A1 - Ostrovskyy, Philip A1 - Piotrowski, Krzysztof A1 - Carta, Corrado A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - A compact one-transistor-multiple-RRAM characterization platform T2 - IEEE transactions on circuits and systems I : regular papers N2 - Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP’s 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 %. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells. KW - RRAM KW - Vector Matrix Multiplication Y1 - 2025 U6 - https://doi.org/10.1109/TCSI.2025.3555234 SN - 1549-8328 SP - 1 EP - 12 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER - TY - GEN A1 - Uhlmann, Max A1 - Rizzi, Tommaso A1 - Wen, Jianan A1 - Quesada, Emilio Pérez-Bosch A1 - Beattie, Bakr Al A1 - Ochs, Karlheinz A1 - Pérez, Eduardo A1 - Ostrovskyy, Philip A1 - Carta, Corrado A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - End-to-end design flow for resistive neural accelerators T2 - IEEE transactions on computer-aided design of integrated circuits and systems N2 - Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed towards leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP’s one-transistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators. KW - RRAM Y1 - 2025 U6 - https://doi.org/10.1109/TCAD.2025.3597237 SN - 0278-0070 SN - 1937-4151 SP - 1 EP - 5 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER -