TY - GEN A1 - Dziallas, Giannino A1 - Fatemi, Adel A1 - Korndörfer, Falk A1 - Peczek, Anna A1 - Kissinger, Dietmar A1 - Zimmermann, Lars A1 - Malignaggi, Andrea A1 - Kahmen, Gerhard T1 - A Monolithically Integrated Optical Bandpass Receiver in 0.25μm SiGe BiCMOS Technology for Microwave-Photonic Applications T2 - 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), November 9-11, 2020 ONLINE Y1 - 2020 SN - 978-1-7281-8436-4 SN - 978-1-7281-8437-1 U6 - https://doi.org/10.1109/A-SSCC48613.2020.9336119 ER - TY - GEN A1 - Fritscher, Markus A1 - Singh, Simranjeet A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Reiser, Daniel A1 - Mallah, Maen A1 - Hartmann, David A1 - Bende, Ankit A1 - Kempen, Tim A1 - Uhlmann, Max A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Rana, Vikas A1 - Menzel, Stephan A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Merchant, Farhad A1 - Wenger, Christian T1 - A flexible and fast digital twin for RRAM systems applied for training resilient neural networks T2 - Scientific Reports N2 - Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT). KW - RRAM KW - Neural network KW - digital twin Y1 - 2024 U6 - https://doi.org/10.1038/s41598-024-73439-z SN - 2045-2322 VL - 14 IS - 1 PB - Springer Science and Business Media LLC ER - TY - GEN A1 - Fritscher, Markus A1 - Uhlmann, Max A1 - Ostrovskyy, Philip A1 - Reiser, Daniel A1 - Chen, Junchao A1 - Schubert, Andreas A1 - Schulze, Carsten A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Wenger, Christian T1 - Area-efficient digital design using RRAM-CMOS standard cells T2 - 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) N2 - Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 % smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 %. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core. KW - RRAM Y1 - 2024 SN - 979-8-3503-5411-9 SN - 979-8-3503-5412-6 U6 - https://doi.org/10.1109/ISVLSI61997.2024.00026 SN - 2159-3477 VL - 18 SP - 81 EP - 87 PB - IEEE ER - TY - GEN A1 - Uhlmann, Max A1 - Rizzi, Tommaso A1 - Wen, Jianan A1 - Pérez-Bosch Quesada, Emilio A1 - Al Beattie, Bakr A1 - Ochs, Karlheinz A1 - Pérez, Eduardo A1 - Ostrovskyy, Philip A1 - Carta, Corrado A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - LUT-based RRAM model for neural accelerator circuit simulation T2 - Proceedings of the 18th ACM International Symposium on Nanoscale Architectures N2 - Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices’ models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP’s 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis. KW - RRAM KW - Neural network Y1 - 2023 U6 - https://doi.org/10.1145/3611315.3633273 SP - 1 EP - 6 PB - ACM CY - New York, NY, USA ER - TY - GEN A1 - Kahmen, Gerhard T1 - SiGe BiCMOS as Enabling Technology for Next Generation RF & THz Systems T2 - EuMIC 2021 Abstract Cards, 16th European Microwave Integrated Circuits Conference (EuMIC), London, United Kingdom, 2022 Y1 - 2022 U6 - https://doi.org/10.23919/EuMIC50153.2022.9783893 SP - S. 21 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Sütbas, Batuhan A1 - Ng, Herman Jalli A1 - Wessel, Jan A1 - Kölpin, Alexander A1 - Kahmen, Gerhard T1 - A V-band Low-Power and Compact Down-Conversion Mixer with Low LO Power in 130-nm SiGe BiCMOS Technology T2 - 16th European Microwave Integrated Circuits Conference (EuMIC), 03-04 April 2022, London, United Kingdom Y1 - 2022 U6 - https://doi.org/10.23919/EuMIC50153.2022.9783953 ER - TY - GEN A1 - Sütbas, Batuhan A1 - Ngy, Herman Jalli A1 - Wessel, Jan A1 - Kölpin, Alexander A1 - Kahmen, Gerhard T1 - Low-Power Ka- and V-Band Miller Compensated Amplifiers in 130-nm SiGe BiCMOS Technology T2 - 16th European Microwave Integrated Circuits Conference (EuMIC), 03-04 April 2022, London, United Kingdom Y1 - 2022 SN - 978-2-87487-064-4 SN - 978-1-6654-4722-5 U6 - https://doi.org/10.23919/EuMIC50153.2022.9783785 ER - TY - GEN A1 - Sütbas, Batuhan A1 - Kahmen, Gerhard T1 - A 7.2-mW V-Band Frequency Doubler with 14% Total Efficiency in 130-nm SiGe BiCMOS T2 - IEEE Microwave and Wireless Components Letters Y1 - 2022 U6 - https://doi.org/10.1109/LMWC.2022.3141557 SN - 1531-1309 SN - 1558-1764 VL - 32 IS - 6 SP - 579 EP - 582 ER - TY - GEN A1 - Dziallas, Giannino A1 - Fatemi, Adel A1 - Peczek, Anna A1 - Zimmermann, Lars A1 - Malignaggi, Andrea A1 - Kahmen, Gerhard T1 - A 56-Gb/s Optical Receiver with 2.08-µA Noise Monolithically Integrated into a 250-nm SiGe BiCMOS Technology T2 - IEEE Transactions on Microwave Theory and Techniques Y1 - 2022 U6 - https://doi.org/10.1109/TMTT.2021.3104838 SN - 0018-9480 SN - 1557-9670 VL - 70 IS - 1 ER - TY - GEN A1 - Eissa, Mohamed Hussein A1 - Fischer, Gunter A1 - Mausolf, Thomas A1 - Rücker, Holger A1 - Malignaggi, Andrea A1 - Kahmen, Gerhard T1 - 220-320-GHz J-Band 4-Way Power Amplifier in Advanced 130-nm BiCMOS Technology T2 - IEEE Microwave and Wireless Components Letters Y1 - 2022 U6 - https://doi.org/10.1109/LMWC.2022.3181407 SN - 1531-1309 SN - 1558-1764 VL - 32 IS - 11 SP - 1335 EP - 1338 ER -