TY - GEN A1 - Vierhaus, Heinrich Theodor A1 - Jenihhin, Maksim A1 - Sonza-Reorda, Matteo T1 - RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality T2 - 2018 Proceedings of the 12th European Workshop on Microelectronics Education (EWME), Braunschweig, 24-26 Sept. 2018 Y1 - 2018 SN - 978-1-5386-9114-4 U6 - https://doi.org/10.1109/EWME.2018.8629465 SP - 45 EP - 50 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Jenihhin, Maksim A1 - Hamdioui, Said A1 - Sonza-Reorda, Matteo A1 - Krstic, Milos A1 - Langendörfer, Peter A1 - Sauer, Christian A1 - Klotz, Anton A1 - Hübner, Michael A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor A1 - Selimis, Georgions A1 - Alexandrescu, Dan A1 - Taouil, Mottaqiallah A1 - Schrijen, Geert-Jan A1 - Sterpone, Luca A1 - Squillero, Giovanni A1 - Dyka, Zoya A1 - Raik, Jaan T1 - RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems T2 - ArXiv.org Y1 - 2019 UR - https://arxiv.org/abs/1912.01561 ER - TY - GEN A1 - Nazari, Samira A1 - Taheri, Mahdi A1 - Azarpeyvand, Ali A1 - Afsharchi, Mohsen A1 - Ghasempouri, Tara A1 - Herglotz, Christian A1 - Daneshtalab, Masoud A1 - Jenihhin, Maksim T1 - FORTUNE : a negative memory overhead hardware-agnostic fault TOleRance techniqUe in DNNs T2 - 2024 IEEE 33rd Asian Test Symposium (ATS) N2 - This paper presents FORTUNE, a hardware-agnostic fault tolerance technique for DNNs that leverages quantization to enhance reliability without significant performance overhead. Unlike conventional methods like Triple Modular Redundancy (TMR), which are computationally expensive, the proposed approach uses memory savings from quantization to protect the critical Most Significant Bit, improving fault tolerance in Deep Neural Networks (DNNs). Memory utilization has been reduced by 37.5% across all networks, with vulnerability in AlexNet reduced by 56% compared to the 8-bit version and 84% compared to the unprotected 3-bit version. These improvements come with only a minor increase in execution time of less than 3%. Using AlexNet as an example demonstrates how our approach effectively enhances memory utilization and resilience while causing only a minimal increase in execution time. Y1 - 2025 SN - 979-8-3315-2917-8 U6 - https://doi.org/10.1109/ATS64447.2024.10915463 SN - 2377-5386 SP - 1 EP - 6 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER - TY - GEN A1 - Nazari, Samira A1 - Taheri, Mahdi A1 - Azarpeyvand, Ali A1 - Afsharchi, Mohsen A1 - Herglotz, Christian A1 - Jenihhin, Maksim T1 - Reliability-aware performance optimization of DNN HW accelerators through heterogeneous quantization T2 - 2025 IEEE 26th Latin American Test Symposium (LATS) N2 - The paper introduces a framework for implementing heterogeneous quantization tailored to individual layers of DNN accelerators. The proposed method, evaluated across DNN benchmarks AlexNet, VGG-11 and ResNet-18, enhances both accuracy drop and performance. On average, the accuracy drop at a BER of 10−4 was reduced by nearly 4 times compared to homogeneous quantization, demonstrating a considerable improvement in reliability under fault-prone conditions. Furthermore, the memory overhead introduced by the method for protected heterogeneous networks is less than 0.1%, highlighting that these reliability gains come with negligible resource costs. Y1 - 2025 SN - 978-1-6654-7763-5 U6 - https://doi.org/10.1109/LATS65346.2025.10963948 SN - 2373-0862 SP - 1 EP - 6 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER -