TY - BOOK A1 - Vierhaus, Heinrich Theodor A1 - Steininger, Andreas A1 - Pawlak, A. A1 - Kraemer, Rolf A1 - Schölzel, Mario A1 - Raik, Jaan T1 - Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems Y1 - 2011 SN - 978-1-4244-9753-9 PB - Piscataway : IEEE, 2011 ER - TY - GEN A1 - Jenihhin, Maksim A1 - Hamdioui, Said A1 - Sonza-Reorda, Matteo A1 - Krstic, Milos A1 - Langendörfer, Peter A1 - Sauer, Christian A1 - Klotz, Anton A1 - Hübner, Michael A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor A1 - Selimis, Georgions A1 - Alexandrescu, Dan A1 - Taouil, Mottaqiallah A1 - Schrijen, Geert-Jan A1 - Sterpone, Luca A1 - Squillero, Giovanni A1 - Dyka, Zoya A1 - Raik, Jaan T1 - RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems T2 - ArXiv.org Y1 - 2019 UR - https://arxiv.org/abs/1912.01561 ER - TY - GEN A1 - Azad, Siavoosh Payandeh A1 - Niazmand, Behrad A1 - Janson, Karl A1 - George, Nevin A1 - Oyeniran, Stephen Adeboye A1 - Putkaradze, Tsotne A1 - Kaur, Apneet A1 - Raik, Jaan A1 - Jervan, Gert A1 - Ubar, Raimund A1 - Hollstein, Thomas T1 - From online fault detection to fault management in Network-on-Chips: A ground-up approach T2 - IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Dresden, Germany, 19-21 April 2017 Y1 - 2017 SN - 978-1-5386-0472-4 SN - 978-1-5386-0473-1 U6 - https://doi.org/10.1109/DDECS.2017.7934565 SN - 2473-2117 ER - TY - GEN A1 - Pappalardo, Salvatore A1 - Bellarmino, Nicolo’ A1 - Deveautour, Bastien A1 - Bosio, Alberto A1 - Taheri, Mahdi A1 - Daneshtalab, Masoud A1 - Raik, Jaan A1 - Jenihhin, Maksim T1 - SAFFIRA : a framework for assessing the reliability of systolic-array DNN accelerators T2 - Journal of circuits, systems, and computers : JCSC N2 - Systolic array has emerged as a prominent architecture for Deep Neural Network (DNN) hardware accelerators, providing high-throughput and low-latency performance essential for deploying DNNs across diverse applications. However, when used in safety-critical applications, reliability assessment is mandatory to guarantee the correct behavior of DNN accelerators. While fault injection stands out as a well-established practical and robust method for reliability assessment, it is still a very time-consuming process. This paper addresses the time efficiency issue by introducing a novel hierarchical software-based hardware-aware fault injection strategy tailored for systolic array-based DNN accelerators. A Uniform Recurrent Equations system is used for software modeling of the systolic-array core of the DNN accelerators. The approach demonstrates a reduction of the fault injection time up to 3× compared to the state-of-the-art hybrid (software/hardware) hardware-aware fault injection frameworks and more than 2000× compared to RT-level fault injection frameworks without compromising the accuracy from the application level. Additionally, we introduce novel reliability metrics to better evaluate the robustness of a deep neural network system. The performance of the framework is studied on state-of-the-art DNN benchmarks. KW - Hardware accelerator KW - Systolic array KW - Deep neural networks KW - Fault simulation reliability KW - Resilience assessment KW - Reliability metrics Y1 - 2025 U6 - https://doi.org/https://doi.org/10.1142/S0218126625430017 SN - 1793-6454 VL - 34 IS - 18 PB - World Scientific CY - Singapore ER -