TY - GEN A1 - Kraatz, Matthias A1 - Gall, Martin A1 - Zschech, Ehrenfried A1 - Schmeißer, Dieter A1 - Ho, Paul S. T1 - A model for statistical electromigration simulation with dependence on capping layer and Cu microstructure in two dimensions T2 - Computational Materials Science N2 - A model has been developed to simulate electromigration degradation in an interconnect segment in two dimensions using finite differences. The model was deployed on a parallel computer to statistically assess the lifetimes. The simulation takes into account the diffusion paths for electromigration mass transport along the grain boundaries and the capping layer. The microstructure is generated with a Monte Carlo algorithm, using a modified Potts model. Diffusivities along the grain boundaries and the capping layers were applied as multiples of a base diffusivity and were statistically scattered. The simulation results correlate well with electromigration tests. KW - Electromigration KW - Grain growth KW - Computer simulation KW - 2D KW - Copper Interconnects KW - On-chip KW - Statistics KW - Parallel computing Y1 - 2016 U6 - https://doi.org/10.1016/j.commatsci.2016.04.020 SN - 1879-0801 SN - 0927-0256 VL - 120 SP - 29 EP - 35 ER - TY - CHAP A1 - Kraatz, Matthias A1 - Zhang, Lijuan A1 - Schmeißer, Dieter A1 - Zschech, Ehrenfried A1 - Ho, Paul S. T1 - Statistical Analysis of Computer-simulated On-Chip Interconnect Electromigration Lifetimes under the Influence of Microstructure and Strengthened Top Interface T2 - Verhandlungen der Deutschen Physikalischen Gesellschaft, Reihe 6, Bd. 46 N2 - We are investigating the statistics of computer-simulated interconnect electromigration (EM) lifetimes with regard to the effects of microstructure and a strengthened top interface. The degradation process of EM once threatened the entire existence of integrated circuit industry in the 1960s and has remained a major reliability concern. Ongoing miniaturization and the introduction of new materials further complicate the task of EM-resistant chip manufacturing. We have developed a simple two-dimensional finite difference simulation that models the mass transport by electromigration along the grain boundaries and the top interface of interconnect segments that allows us to do calculations of void nucleation and growth. A parallel computer simulates hundreds of interconnects simultaneously and statistical analysis becomes feasible. A Monte Carlo grain growth algorithm (a modified Potts version) is applied to model the grain structure of the interconnect segments. We will show that the simulation can be used to compare simulation and experiment qualitatively. Four cases have been studied: interconnect segments with small/large grains and weak/strong top interface. Y1 - 2011 UR - http://www.dpg-verhandlungen.de/year/2011/conference/dresden/part/ds/session/7/contribution/2 SN - 0420-0195 SP - S. 292 PB - Deutsche Physikalische Gesellschaft CY - Bad Honnef ER - TY - CHAP A1 - Kraatz, Matthias A1 - Schmeißer, Dieter A1 - Zschech, Ehrenfried A1 - Ho, Paul S. T1 - Electromigration simulation for on-chip Cu interconnects T2 - Verhandlungen der Deutschen Physikalischen Gesellschaft, Reihe 6, Bd. 44 N2 - We are investigating the influence of copper microstructure on electromigration degradation effects and interconnect lifetimes using computer simulation. The simulation is carried out in three dimensions. For the copper microstructure, a Monte Carlo technique was used to model the Cu grain growth. Different diffusivities where applied to grain boundaries and top interface of the interconnect model according to the qualitative crystallographic orientation of adjacent grains. The grain boundary network and the top interface form the diffusion paths for the electromigration mass transport. Along the diffusion paths, the fluxes of vacancies where calculated including mechanical stress and electromigration driving forces using a finite difference method. Positive flux divergent sites of the FDM lattice are treated as void nucleation sites after a critical vacancy concentration is reached. The resistance increase due to void growth was calculated using a cellular automaton, masking current free regions as quasi voids and adding the resistance of the slices of the lattice normal to the electron flow direction in series. A parallel computing environment was used to generate large numbers of interconnect models in order to obtain a pool of data for statistical analysis of interconnect lifetimes. The results of this analysis will be shown Y1 - 2009 UR - http://www.dpg-verhandlungen.de/year/2009/conference/dresden/part/ds/session/13/contribution/4 SN - 0420-0195 SP - S. 161 PB - Deutsche Physikalische Gesellschaft CY - Bad Honnef ER - TY - GEN A1 - Ho, Paul S. A1 - Zschech, Ehrenfried A1 - Schmeißer, Dieter A1 - Meyer, Moritz Andreas A1 - Huebner, Rene A1 - Hauschildt, Meike A1 - Zhang, Lijuan A1 - Gall, Martin A1 - Kraatz, Matthias T1 - Scaling effects on microstructure and reliability for cu interconnects KW - scaling KW - microstructure KW - interconnects Y1 - 2010 ER -