TY - GEN A1 - Pechmann, Stefan A1 - Mai, Timo A1 - Völkel, Matthias A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Pérez, Eduardo A1 - Perez-Bosch Quesada, Emilio A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Hagelauer, Amelie T1 - A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells T2 - Electronics N2 - In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9. KW - RRAM KW - Multilevel switching KW - Programming circuit Y1 - 2021 U6 - https://doi.org/10.3390/electronics10050530 SN - 2079-9292 VL - 10 IS - 5 ER - TY - GEN A1 - Pechmann, Stefan A1 - Mai, Timo A1 - Potschka, Julian A1 - Reiser, Daniel A1 - Reichel, Peter A1 - Breiling, Marco A1 - Reichenbach, Marc A1 - Hagelauer, Amelie T1 - A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks T2 - Micromachines Y1 - 2021 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:bvb:29-opus4-174878 SN - 2072-666X VL - 12 IS - 11 ER - TY - GEN A1 - Pechmann, Stefan A1 - Pérez, Eduardo A1 - Wenger, Christian A1 - Hagelauer, Amelie T1 - A current mirror Based read circuit design with multi-level capability for resistive switching deviceb T2 - 2024 International Conference on Electronics, Information, and Communication (ICEIC) N2 - This paper presents a read circuit design for resistive memory cells based on current mirrors. The circuit utilizes high-precision current mirrors and reference cells to determine the state of resistive memory using comparators. It offers a high degree in adaptability in terms of both resistance range and number of levels. Special emphasis was put on device protection to prevent accidental programming of the memory during read operations. The realized circuit can resolve eight states with a resolution of up to 1 k Ω, realizing a digitization of the analog memory information. Furthermore, the integration in a complete memory macro is shown. The circuit was realized in a 130 nm-process but can easily be adapted to other processes and resistive memory technologies. KW - RRAM KW - memristive device Y1 - 2024 SN - 979-8-3503-7188-8 U6 - https://doi.org/10.1109/ICEIC61013.2024.10457188 SN - 2767-7699 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Jia, Ruolan A1 - Pechmann, Stefan A1 - Markus, Fritscher A1 - Wenger, Christian A1 - Zhang, Lei A1 - Hagelauer, Amelie T1 - Soft-Error Analysis of RRAM 1T1R Compute-In-Memory Core for Artificial Neural Networks T2 - 2024 39th Conference on Design of Circuits and Integrated Systems (DCIS) N2 - This work analyses SEU-induced soft-errors in analog compute-in-memory cores using resistive random-access memory (RRAM) for artificial neural networks, where their bitcells utilize one-transistor-one-RRAM (1T1R) structure. This is modeled by combining the Stanford-PKU RRAM Model and the model of the radiation-induced photocurrent in access transistors. As results, this work derives the maximal RRAM crossbar size without occurring any logic flip and indicates the requirements for RRAM technology to achieve a SEU-resilient 1T1R compute-in memory cores. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1109/DCIS62603.2024.10769203 SP - 1 EP - 5 PB - IEEE ER - TY - GEN A1 - Vishwakarma, Abhinav A1 - Fritscher, Markus A1 - Hagelauer, Amelie A1 - Reichenbach, Marc T1 - An RRAM-based building block for reprogrammable non-uniform sampling ADCs T2 - Information Technology : it Y1 - 2023 U6 - https://doi.org/10.1515/itit-2023-0021 SN - 2196-7032 VL - 65 IS - 1-2 SP - 39 EP - 51 ER - TY - GEN A1 - Perez-Bosch Quesada, Emilio A1 - Rizzi, Tommaso A1 - Gupta, Aditya A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Schubert, Andreas A1 - Pechmann, Stefan A1 - Jia, Ruolan A1 - Uhlmann, Max A1 - Hagelauer, Amelie A1 - Wenger, Christian A1 - Pérez, Eduardo T1 - Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing T2 - 14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023 N2 - This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications. Index Terms—radiation-hard, hardness-by-design, memristive devices, Enclosed Layout Transistor, in-memory computing KW - RRAM Y1 - 2023 SN - 979-8-3503-0240-0 U6 - https://doi.org/10.1109/CDE58627.2023.10339525 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Perez, Eduardo A1 - Maldonado, David A1 - Pechmann, Stefan A1 - Reddy, Keerthi Dorai Swamy A1 - Uhlmann, Max A1 - Hagelauer, Amelie A1 - Roldan, Juan Bautista A1 - Wenger, Christian T1 - Impact of the series resistance on switching characteristics of 1T1R HfO₂-based RRAM devices T2 - 2025 15th Spanish Conference on Electron Devices (CDE) N2 - This study investigates the influence of the series resistance (RS) on the switching characteristics of 1-transistor-1-resistor (1T1R) RRAM devices based on HfO2 and Al:HfO₂ dielectrics. Intrinsic RS values were extracted from I-V characteristics measured over 50 Reset-Set cycles at various gate voltages (VG) by using a numerical transformation method. Results reveal the contribution of the transistor’s resistance to the overall RS. A linear relationship between RS values and Set transition voltages (VTS) was found, with larger RS values amplifying the variability in switching parameters. Comparative analysis of cumulative distribution functions (CDFs) highlights differences between technologies, showing lower VTS values as well as lower sensitivity to RS for Al:HfO₂-based devices. These findings underscore the critical role of RS in modeling and optimizing the performance of RRAM devices for reliable operation. KW - RRAM KW - Memristive device Y1 - 2025 SN - 979-8-3315-9618-7 U6 - https://doi.org/10.1109/CDE66381.2025.11038868 SP - 1 EP - 4 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - Piscataway, NJ ER -