TY - GEN A1 - Bielefeldt, Jens A1 - Basener, Kai-Uwe A1 - Khan, Siddique R. A1 - Massah, Mozhdeh A1 - Wiesbrock, Hans-Werner A1 - Scharoba, Stefan A1 - Hübner, Michael T1 - Einsatz von Deep Learning für den Test Eingebetteter Systeme  T2 - Informatik 2021: computer science & sustainability, 27. September-01. Oktober 2021, Berlin Y1 - 2021 SN - 978-3-88579-708-1 U6 - https://doi.org/10.18420/INFORMATIK2021-166 PB - Gesellschaft für Informatik e.V. CY - Bonn ER - TY - GEN A1 - Mahmood, Safdar A1 - Scharoba, Stefan A1 - Schorlemer, Jonas A1 - Schulz, Christian A1 - Hübner, Michael A1 - Reichenbach, Marc T1 - Detecting Improvised Land-mines using Deep Neural Networks on GPR Image Dataset targeting FPGAs  T2 - IEEE Nordic Circuits and Systems Conference (NORCAS), 25-26 October 2022, Oslo, Norway Y1 - 2022 SN - 979-8-3503-4550-6 SN - 979-8-3503-4551-3 U6 - https://doi.org/10.1109/norcas57515.2022.9934735 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Mahmood, Safdar A1 - Hübner, Michael A1 - Reichenbach, Marc ED - Palumbo, Francesca ED - Keramidas, Georgios ED - Voros, Nikolaos ED - Diniz, Pedro C. T1 - A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023 Y1 - 2023 SN - 978-3-031-42921-7 SN - 978-3-031-42920-0 U6 - https://doi.org/10.1007/978-3-031-42921-7_27 SP - 371 EP - 374 PB - Springer CY - Cham ER - TY - GEN A1 - Da Silva, Samuel Souza A1 - Cardoso, Matheus A1 - Nardo, Lucas A1 - Nepomuceno, Erivelton A1 - Hübner, Michael A1 - Arias-Garcia, Janier T1 - A New Chaos-Based PRNG Hardware Architecture Using The HUB Fixed-Point Format T2 - IEEE Transactions on Instrumentation and Measurement Y1 - 2023 U6 - https://doi.org/10.1109/TIM.2023.3235457 SN - 1557-9662 SN - 0018-9456 VL - Vol. 72 SP - 1 EP - 8 ER - TY - GEN A1 - Shahin, Keyvan A1 - Hübner, Michael A1 - Herglotz, Christian T1 - A width-configurable hardware approach for accelerating fixed-point simulation T2 - IEEE Computer Society Annual Symposium on VLSI (ISVLSI) N2 - Fixed-point simulation is a critical step in the design flow of Digital Signal Processing (DSP) systems and consumes a significant portion of the overall development time. This work proposes a novel hardware-based approach to improve the performance of fixed-point simulation through a widthconfigurable architecture implemented on Field-Programmable Gate Arrays (FPGAs). To our knowledge, this is the first reported hardware-based solution for fixed-point simulation reported in the literature, which provides substantial speedup compared to traditional software-based approaches. The presented approach utilizes High-Level Synthesis (HLS) tools to create modular, reusable components that enhance the design reusability. This approach accelerates fixed-point simulation for various applications, requiring only minor modifications to the application code to utilize it. By incorporating simulation capabilities within reusable functions, this work improves the efficiency and adaptability of the fixed-point simulation process. Implementation results for two FIR filter applications show that the proposed methodology is superior to traditional software-based approaches in reducing simulation time by two orders of magnitude and thus has the potential to improve the productivity of the DSP system design flow. KW - Fixed-Point Simulation, Width-Configurable Hardware, Hardware-based Acceleration, High-Level Synthesis (HLS) Y1 - 2025 SN - 979-8-3315-3477-6 U6 - https://doi.org/10.1109/ISVLSI65124.2025.11130205 SN - 2159-3477 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Shahin, Keyvan A1 - Hübner, Michael T1 - Accelerating fixed-point simulations using width reconfigurable hardware architectures T2 - 31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 30 August-3 September 2021 N2 - Digital Signal Processing (DSP) systems can be described using either fixed-point or floating-point for their numeric representations. As the general computers use floating-point representation, software-based simulation tools used for modeling and simulation of the arithmetic operations in DSP systems, use floating-point representation as well. However, synthesizing customized hardware for fixed-point arithmetic operations for FPGAs or ASICs is more efficient compared to their floating-point counterparts. Thus it is necessary to convert the representation of a floating-point simulated algorithm on MATLAB for example, to a fixed-point representation which is more suitable for hardware implementation. While former approaches for this conversion step have always been software-based, like on MATLAB itself, this paper presents a new approach to show the possibility of accelerating it by using hardware width reconfigurable designs. KW - Computers, Computational modeling , Signal processing algorithms, Digital signal processing, Tools, Hardware, Numerical models Y1 - 2021 SN - 978-1-6654-3759-2 U6 - https://doi.org/10.1109/FPL53798.2021.00055 SN - 1946-1488 SP - 275 EP - 276 PB - IEEE CY - Piscataway, NJ ER -