TY - GEN A1 - Brandalero, Marcelo A1 - Veleski, Mitko A1 - Muñoz-Hernandez, Hector Gerardo A1 - Ali, Muhammad A1 - Le Jeune, Laurens A1 - Goedemé, Toon A1 - Mentens, Nele A1 - Vandendriessche, Jurgen A1 - Lhoest, Lancelot A1 - Da Silva, Bruno A. A1 - Touhafi, Abdellah A1 - Goehringer, Diana A1 - Hübner, Michael T1 - Embedded AI Techniques for Industrial Applications T2 - 31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 30 August-3 September 2021 Y1 - 2021 SN - 978-1-6654-3759-2 U6 - https://doi.org/10.1109/FPL53798.2021.00071 SP - 374 EP - 375 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Giani, Braga A1 - Benevenuti, Fabio A1 - Gonçalves, Marcio M. A1 - Hübner, Michael A1 - Brandalero, Marcelo A1 - Kastensmidt, Fernanda A1 - Azambuja, Jose Rodrigo T1 - Evaluating softcore GPU in SRAM-based FPGA under radiation-induced effects T2 - Microelectronics Reliability Y1 - 2021 U6 - https://doi.org/10.1016/j.microrel.2021.114348 SN - 0026-2714 SN - 1872-941X VL - 126 ER - TY - GEN A1 - Gonçalves, Marcio M. A1 - Benevenuti, Fabio A1 - Munoz-Hernandez, Hector Gerardo A1 - Brandalero, Marcelo A1 - Hübner, Michael A1 - Kastensmidt, Fernanda A1 - Azambuja, Jose Rodrigo T1 - Investigating Floating-Point Implementations in a Softcore GPU under Radiation-Induced Faults T2 - 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), virtual conference, November 23-25, 2020 Y1 - 2020 SN - 978-1-7281-6044-3 SN - 978-1-7281-6045-0 U6 - https://doi.org/10.1109/ICECS49266.2020.9294939 SP - 1 EP - 4 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Brandalero, Marcelo A1 - Ali, Muhammad A1 - Le Jeune, Laurens A1 - Munoz-Hernandez, Hector Gerardo A1 - Veleski, Mitko A1 - Silva, Bruno da A1 - Lemeire, Jan A1 - Van Beeck, Kristof A1 - Touhafi, Abdellah A1 - Goedemé, Toon A1 - Mentens, Nele A1 - Göhringer, Diana A1 - Hübner, Michael T1 - AITIA: Embedded AI Techniques for Industrial Applications T2 - International Conference on Omni-Layer Intelligent Systems (COINS), 31 August-2 September 2020, Barcelona, Spain Y1 - 2020 SN - 978-1-7281-6371-0 U6 - https://doi.org/10.1109/COINS49042.2020.9191672 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Assafo, Maryam A1 - Lautsch, Martin A1 - Suawa, Priscile Fogou A1 - Jongmanns, Marcel A1 - Hübner, Michael A1 - Reichenbach, Marc A1 - Brockmann, Carsten A1 - Reinhardt, Denis A1 - Langendörfer, Peter T1 - The ForTune Toolbox: Building Solutions for Condition-Based and Predictive Maintenance Focusing on Retrofitting Y1 - 2023 SN - 978-3-8007-6204-0 SN - 978-3-8007-6203-3 N1 - Poster, Tagungsband MikroSystemTechnik Kongress 2023, Dresden, 23. - 25. Oktober 2023 SP - S. 541 PB - VDE Verlag CY - Berlin ER - TY - GEN A1 - Veleski, Mitko A1 - Hübner, Michael A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Design and implementation strategy of adaptive processor-based systems for error resilient and power-efficient operation T2 - 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS, April 7-9 2021 Y1 - 2021 SN - 978-1-6654-3595-6 U6 - https://doi.org/10.1109/DDECS52668.2021.9417023 SP - 57 EP - 62 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Veleski, Mitko A1 - Hübner, Michael A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Towards Error Resilient and Power-Efficient Adaptive Multiprocessor System using Highly Configurable and Flexible Cross-Layer Framework T2 - IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), IOLTS 2021, June 28-30, 2021 Y1 - 2021 SN - 978-1-6654-3370-9 U6 - https://doi.org/10.1109/IOLTS52814.2021.9486695 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Bielefeldt, Jens A1 - Basener, Kai-Uwe A1 - Khan, Siddique R. A1 - Massah, Mozhdeh A1 - Wiesbrock, Hans-Werner A1 - Scharoba, Stefan A1 - Hübner, Michael T1 - DeepTest: How Machine Learning Can Improve the Test of Embedded Systems  T2 - 10th Mediterranean Conference on Embedded Computing (MECO), 7-10 June 2021 Y1 - 2021 SN - 978-1-6654-3912-1 SN - 978-1-6654-2989-4 U6 - https://doi.org/10.1109/meco52532.2021.9460182 SP - 1 EP - 6 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Scharoba, Stefan A1 - Basener, Kai-Uwe A1 - Bielefeldt, Jens A1 - Wiesbrock, Hans-Werner A1 - Hübner, Michael T1 - Towards Machine Learning Support for Embedded System Tests T2 - 24th Euromicro Conference on Digital System Design, DSD 2021, virtual conference, 1-3 September 2021 Y1 - 2021 SN - 978-1-6654-2703-6 SN - 978-1-6654-2704-3 U6 - https://doi.org/10.1109/dsd53832.2021.00034 SP - 166 EP - 173 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Bielefeldt, Jens A1 - Basener, Kai-Uwe A1 - Khan, Siddique R. A1 - Massah, Mozhdeh A1 - Wiesbrock, Hans-Werner A1 - Scharoba, Stefan A1 - Hübner, Michael T1 - Einsatz von Deep Learning für den Test Eingebetteter Systeme  T2 - Informatik 2021: computer science & sustainability, 27. September-01. Oktober 2021, Berlin Y1 - 2021 SN - 978-3-88579-708-1 U6 - https://doi.org/10.18420/INFORMATIK2021-166 PB - Gesellschaft für Informatik e.V. CY - Bonn ER - TY - GEN A1 - Mahmood, Safdar A1 - Scharoba, Stefan A1 - Schorlemer, Jonas A1 - Schulz, Christian A1 - Hübner, Michael A1 - Reichenbach, Marc T1 - Detecting Improvised Land-mines using Deep Neural Networks on GPR Image Dataset targeting FPGAs  T2 - IEEE Nordic Circuits and Systems Conference (NORCAS), 25-26 October 2022, Oslo, Norway Y1 - 2022 SN - 979-8-3503-4550-6 SN - 979-8-3503-4551-3 U6 - https://doi.org/10.1109/norcas57515.2022.9934735 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Mahmood, Safdar A1 - Hübner, Michael A1 - Reichenbach, Marc ED - Palumbo, Francesca ED - Keramidas, Georgios ED - Voros, Nikolaos ED - Diniz, Pedro C. T1 - A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023 Y1 - 2023 SN - 978-3-031-42921-7 SN - 978-3-031-42920-0 U6 - https://doi.org/10.1007/978-3-031-42921-7_27 SP - 371 EP - 374 PB - Springer CY - Cham ER - TY - GEN A1 - Da Silva, Samuel Souza A1 - Cardoso, Matheus A1 - Nardo, Lucas A1 - Nepomuceno, Erivelton A1 - Hübner, Michael A1 - Arias-Garcia, Janier T1 - A New Chaos-Based PRNG Hardware Architecture Using The HUB Fixed-Point Format T2 - IEEE Transactions on Instrumentation and Measurement Y1 - 2023 U6 - https://doi.org/10.1109/TIM.2023.3235457 SN - 1557-9662 SN - 0018-9456 VL - Vol. 72 SP - 1 EP - 8 ER - TY - GEN A1 - Shahin, Keyvan A1 - Hübner, Michael A1 - Herglotz, Christian T1 - A width-configurable hardware approach for accelerating fixed-point simulation T2 - IEEE Computer Society Annual Symposium on VLSI (ISVLSI) N2 - Fixed-point simulation is a critical step in the design flow of Digital Signal Processing (DSP) systems and consumes a significant portion of the overall development time. This work proposes a novel hardware-based approach to improve the performance of fixed-point simulation through a widthconfigurable architecture implemented on Field-Programmable Gate Arrays (FPGAs). To our knowledge, this is the first reported hardware-based solution for fixed-point simulation reported in the literature, which provides substantial speedup compared to traditional software-based approaches. The presented approach utilizes High-Level Synthesis (HLS) tools to create modular, reusable components that enhance the design reusability. This approach accelerates fixed-point simulation for various applications, requiring only minor modifications to the application code to utilize it. By incorporating simulation capabilities within reusable functions, this work improves the efficiency and adaptability of the fixed-point simulation process. Implementation results for two FIR filter applications show that the proposed methodology is superior to traditional software-based approaches in reducing simulation time by two orders of magnitude and thus has the potential to improve the productivity of the DSP system design flow. KW - Fixed-Point Simulation, Width-Configurable Hardware, Hardware-based Acceleration, High-Level Synthesis (HLS) Y1 - 2025 SN - 979-8-3315-3477-6 U6 - https://doi.org/10.1109/ISVLSI65124.2025.11130205 SN - 2159-3477 PB - IEEE CY - Piscataway, NJ ER -