TY - CHAP A1 - Kästner, Florian A1 - Janßen, Benedikt A1 - Kautz, Frederik A1 - Hübner, Michael A1 - Corradi, Giulio T1 - Hardware/Software Codesign for Convolutional Neural Networks exploiting Dynamic Partial Reconfiguration on PYNQ T2 - 32nd International Parallel and Distributed Processing Symposium workshops, IPDPSW 2018, proceedings, 21-25 May 2018, Vancouver, British Columbia, Canada Y1 - 2018 UR - https://ieeexplore.ieee.org/abstract/document/8425398 SN - 978-1-5386-5555-9 SP - 154 EP - 161 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Janßen, Benedikt A1 - Kästner, Florian A1 - Wingender, Tim A1 - Hübner, Michael ED - Voros, Nikolaos ED - Hübner, Michael ED - Keramidas, Georgios ED - Göhringer, Diana ED - Antonopoulos, Christos ED - Diniz, Pedro C. T1 - A Dynamic Partial Reconfigurable Overlay Framework for Python T2 - Proceedings, 14th International Symposium on Applied Reconfigurable Computing, Santorini, Greece, May 2-4, 2018 Y1 - 2018 SN - 978-3-319-78889-0 SN - 978-3-319-78890-6 SP - 331 EP - 342 PB - Springer CY - Cham ER - TY - CHAP A1 - Guzman, Osvaldo Navarro A1 - Hübner, Michael ED - Voros, Nikolaos ED - Hübner, Michael ED - Keramidas, Georgios ED - Göhringer, Diana ED - Antonopoulos, Christos ED - Diniz, Pedro C. T1 - Runtime Adaptive Cache for the LEON3 Processor T2 - Proceedings, 14th International Symposium on Applied Reconfigurable Computing, Santorini, Greece, May 2-4, 2018 Y1 - 2018 SP - 343 EP - 354 PB - Springer CY - Cham ER - TY - CHAP A1 - Janßen, Benedikt A1 - Kästner, Florian A1 - Kautz, Frederik A1 - Hübner, Michael ED - Hübner, Michael ED - Rückemann, Claus-Peter T1 - Exploring Deep Neural Networks for Regression Analysis T2 - PESARO 2018, the Eighth International Conference on Performance, Safety and Robustness in Complex Systems and Applications, April 22-26, 2018, Athens, Greece / Y1 - 2018 SN - 978-1-61208-628-6 PB - IARIA CY - [Wilmington] ER - TY - CHAP A1 - Keramidas, Georgios A1 - Antonopoulos, Christos A1 - Voros, Nikolaos A1 - Schwiegelshohn, Fynn A1 - Wehner, Philipp A1 - Rettkowski, Jens A1 - Göhringer, Diana A1 - Hübner, Michael A1 - Konstantopoulos, Stasinos A1 - Giannakopoulos, Theodore A1 - Karkaletsis, Vangelis A1 - Mariatos, Vaggelis T1 - Computation and Communication Challenges to Deploy Robots in Assisted Living Environments T2 - Design, Automation & Test in Europe Conference & Exhibition (DATE), 14-18 March 2016 Dresden, Germany Y1 - 2016 UR - https://ieeexplore.ieee.org/document/7459434 SN - 978-3-9815370-7-9 SP - 888 EP - 893 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Mori Alves da Silva, Jones Yudi A1 - Werner, André A1 - Shallufa, Arij A1 - Fricke, Florian A1 - Hübner, Michael T1 - A Design Methodology for the Next Generation Real-Time Vision Processors T2 - Applied reconfigurable computing, 12th international symposium, ARC 2016, Mangaratiba, RJ, Brazil, March 22-24, 2016 Y1 - 2016 SN - 978-3-319-30480-9 SN - 978-3-319-30481-6 SP - 14 EP - 25 PB - Springer CY - Cham ER - TY - CHAP A1 - Mori Alves da Silva, Jones Yudi A1 - Werner, André A1 - Fricke, Florian A1 - Hübner, Michael T1 - A rapid prototyping method to reduce the design time in commercial high-level synthesis tools T2 - 23rd Re­con­fi­gura­ble Ar­chi­tec­tu­res Work­shop (RAW 2016), Chi­ca­go, USA Y1 - 2016 SN - 978-1-5090-3682-0 SP - 253 EP - 258 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Mori Alves da Silva, Jones Yudi A1 - Kautz, Frederik A1 - Hübner, Michael T1 - Efficient Camera Input System and Memory Partition for a Vision Soft-Processor T2 - Applied reconfigurable computing, 12th international symposium, ARC 2016, Mangaratiba, RJ, Brazil, March 22-24, 2016 Y1 - 2016 SN - 978-3-319-30480-9 SN - 978-3-319-30481-6 SP - 328 EP - 333 PB - Springer CY - Cham ER - TY - CHAP A1 - Schwiegelshohn, Fynn A1 - Kästner, Florian A1 - Hübner, Michael T1 - Enabling Dynamic Reconfiguration of Numerical Methods for the Robotic Motion Control Task T2 - 23rd Re­con­fi­gura­ble Ar­chi­tec­tu­res Work­shop (RAW 2016), Chi­ca­go, USA Y1 - 2016 SN - 978-1-5090-3682-0 SP - 283 EP - 288 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Janßen, Benedikt A1 - Naserddin, Moataz A1 - Hübner, Michael T1 - A Hardware/Software Co-Design Approach for Control Applications with Static Real-Time Reallocation T2 - 23rd Re­con­fi­gura­ble Ar­chi­tec­tu­res Work­shop (RAW 2016), Chi­ca­go, USA Y1 - 2016 SN - 978-1-5090-3682-0 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Al Kadi, Muhammed Soubhi A1 - Janßen, Benedikt A1 - Hübner, Michael T1 - FGPU: An SIMT-Architecture for FPGAs T2 - FPGA '16 Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA — February 21 - 23, 2016 Y1 - 2016 SN - 978-1-4503-3856-1 SN - 978-1-4503-4468-5 SP - 254 EP - 263 PB - ACM, Association for Computing Machinery CY - New York, NY ER - TY - GEN A1 - Schwiegelshohn, Fynn A1 - Ossovski, Eugen A1 - Hübner, Michael T1 - A resampling method for parallel particle filter architectures T2 - Microprocessors & Microsystems Y1 - 2016 U6 - https://doi.org/10.1016/j.micpro.2016.07.017 SN - 0141-9331 VL - 47, B SP - 314 EP - 320 ER - TY - CHAP A1 - Fricke, Florian A1 - Werner, André A1 - Shahin, Keyvan A1 - Hübner, Michael ED - Voros, Nikolaos ED - Hübner, Michael ED - Keramidas, Georgios ED - Göhringer, Diana ED - Antonopoulos, Christos ED - Diniz, Pedro C. T1 - CGRA Tool Flow for Fast Run-Time Reconfiguration T2 - Proceedings, 14th International Symposium on Applied Reconfigurable Computing, Santorini, Greece, May 2-4, 2018 Y1 - 2018 SN - 978-3-319-78889-0 SN - 978-3-319-78890-6 U6 - https://doi.org/10.1007/978-3-319-78890-6_53 SP - 661 EP - 672 PB - Springer CY - Cham ER - TY - GEN A1 - Glock, Thomas A1 - Kern, Matthias A1 - Otten, Stefan A1 - Sax, Eric A1 - Hillenbrand, Martin A1 - Hübner, Michael T1 - Prozessanlagenplanung 2.0 Netzarchitektur aus Vefahrensbeschreibung ableiten T2 - atp edition Y1 - 2016 SN - 2190-4111 VL - 58 IS - 10 SP - 28 EP - 39 ER - TY - CHAP A1 - Grimm, Tomas A1 - Lettnin, Djones A1 - Hübner, Michael T1 - Automatic Generation of RTL Connectivity Checkers for Automotive Gateways from SystemC TLM Models T2 - IEEE Nordic Circuits and Systems Conference, 1-2 November 2016, Copenhagen, Denmark Y1 - 2017 SN - 978-1-5090-1095-0 U6 - https://doi.org/10.1109/NORCHIP.2016.7792922 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Schwiegelshohn, Fynn A1 - Kästner, Florian A1 - Hübner, Michael T1 - FPGA design of numerical methods for the robotic motion control task exploiting high-level synthesis T2 - IEEE International Conference on the Science of Electrical Engineering (ICSEE), 16-18 Nov. 2016, Eilat, Israel Y1 - 2016 UR - https://ieeexplore.ieee.org/document/7806074 SN - 978-1-5090-2152-9 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Fricke, Florian A1 - Werner, André A1 - Janßen, Benedikt A1 - Hübner, Michael A1 - Ribbe, Clemens A1 - Cengizhan, Inac T1 - Redesign of an Educational Robot Platform Using Web-based Programming T2 - Proceedings of the 2016 Workshop on Embedded and Cyber-Physical Systems Education, Pittsburgh, PA, USA - October 01-07, 2016 Y1 - 2016 SN - 978-1-4503-4657-3 U6 - https://doi.org/10.1145/3005329.3005332 PB - ACM CY - New York, NY ER - TY - CHAP A1 - Janßen, Benedikt A1 - Wehner, Philipp A1 - Göhringer, Diana A1 - Hübner, Michael T1 - Development of Advanced Driver Assistance Systems using LabVIEW and a Car Simulator T2 - Proceedings of the 2016 Workshop on Embedded and Cyber-Physical Systems Education, Pittsburgh, PA, USA - October 01-07, 2016 Y1 - 2016 SN - 978-1-4503-4657-3 U6 - https://doi.org/10.1145/3005329.3005330 PB - ACM CY - New York, NY ER - TY - CHAP A1 - Mori Alves da Silva, Jones Yudi A1 - Hübner, Michael T1 - Multi-level parallelism analysis and system-level simulation for many-core vision processor design T2 - 5th Mediterranean Conference on Embedded Computing (MECO), Bar, Montenegro, June 12th-16th Y1 - 2016 UR - https://ieeexplore.ieee.org/document/7525710 SN - 978-1-5090-2222-9 SP - 90 EP - 95 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Glock, Thomas A1 - Hillenbrand, Martin A1 - Hübner, Michael T1 - Smarte Sensoren in der Feldebene T2 - atp edition Y1 - 2015 SN - 2364-3137 VL - 57 IS - 11 SP - 32 EP - 42 ER - TY - CHAP A1 - Lalevée, André A1 - Horrein, Pierre-Henri A1 - Arzel, Matthieu A1 - Hübner, Michael A1 - Vaton, Sandrine T1 - AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs T2 - DSD 2016, proceedings, 19th Euromicro Conference in Digital System Design, 31 August-2 September 2016, Limassol, Cyprus Y1 - 2016 SN - 978-1-5090-2817-7 U6 - https://doi.org/10.1109/DSD.2016.92 SP - 14 EP - 21 PB - IEEE CY - Piscataway, NJ ER -