TY - GEN A1 - Hoffmann, Javier Eduardo A1 - Kuschnerus, Dirk A1 - Jones, Trevor A1 - Hübner, Michael T1 - Towards a Safety and Energy Aware protocol for Wireless Communication T2 - 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Lille Y1 - 2018 SN - 978-1-5386-7957-9 SN - 978-1-5386-7958-6 U6 - https://doi.org/10.1109/ReCoSoC.2018.8449380 PB - Piscataway, NJ CY - IEEE ER - TY - GEN A1 - Kästner, Florian A1 - Guzman, Osvaldo Navarro A1 - Jan­ßen, Be­ne­dikt A1 - Hoffmann, Javier Eduardo A1 - Hübner, Michael T1 - Analysis of Hardware Implementations to Accelerate Convolutional and Recurrent Neuronal Net­works T2 - In­ter­na­tio­nal Jour­nal on Ad­van­ces in Soft­ware Y1 - 2017 UR - http://www.iariajournals.org/software/soft_v10_n34_2017_paged.pdf SN - 1942-2628 VL - 10 IS - 3/4 SP - 308 EP - 323 PB - IARIA ER - TY - GEN A1 - Hoffmann, Javier Eduardo A1 - Guzman, Osvaldo Navarro A1 - Kästner, Florian A1 - Jan­ßen, Be­ne­dikt A1 - Hübner, Michael T1 - A survey on CNN and RNN implementations T2 - PE­SA­RO 2017, The Seventh In­ter­na­tio­nal Con­fe­rence on Per­for­mance, Sa­fe­ty and Ro­bust­ness in Com­plex Sys­tems and Ap­p­li­ca­ti­ons Y1 - 2017 SN - 978-1-61208-549-4 SP - 33 EP - 39 PB - IARIA CY - Wilmington, DE, USA ER - TY - GEN A1 - Antonopoulos, Christos A1 - Keramidas, Georgios A1 - Voros, Nikolaos A1 - Hübner, Michael A1 - Schwiegelshohn, Fynn A1 - Göhringer, Diana A1 - Dagioglou, Maria A1 - Stavrinos, Georgios A1 - Konstantopoulos, Stasinos A1 - Karkaletsis, Vangelis T1 - Toward an ICT-Based Service Oriented Health Care Paradigm T2 - IEEE Consumer Electronics Magazine Y1 - 2020 UR - https://ieeexplore.ieee.org/abstract/document/9109415 U6 - https://doi.org/10.1109/MCE.2020.2969202 SN - 2162-2248 SN - 2162-2256 VL - 9 IS - 4 SP - 77 EP - 82 PB - IEEE ER - TY - GEN A1 - Hübner, Michael A1 - Guntzel, Jose Luis T1 - Guest Editors’ Introduction: SBCCI 2018 T2 - IEEE Design & Test Y1 - 2020 U6 - https://doi.org/10.1109/MDAT.2020.2989094 SN - 2168-2364 SN - 2168-2356 VL - 37 IS - 3 SP - 5 EP - 6 ER - TY - GEN A1 - Fouad, Mariam A1 - Metwally, Yousef A1 - Schmitz, Georg A1 - Hübner, Michael A1 - Abd El Ghany, Mohamed A. T1 - Deep Learning Utilization In Beamforming Enhancement for Medical Ultrasound T2 - 2020 IEEE 44th Annual Computers, Software, and Applications Conference (COMPSAC), 13-17 July 2020, Madrid, Spain Y1 - 2020 SN - 978-1-7281-7303-0 U6 - https://doi.org/10.1109/COMPSAC48688.2020.0-175 SP - 717 EP - 722 PB - IEEE ER - TY - GEN A1 - Hoffmann, Javier Eduardo A1 - Mahmood, Safdar A1 - Suawa Fogou, Priscile A1 - George, Nevin A1 - Raha, Solaiman A1 - Safi, Sabur A1 - Schmailzl, Kurt JG A1 - Brandalero, Marcelo A1 - Hübner, Michael T1 - A Survey on Machine Learning Approaches to ECG Processing T2 - 2020 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), 23-25 Sept. 2020 , Poznan, Poland Y1 - 2020 UR - https://ieeexplore.ieee.org/document/9241283 SN - 978-83-62065-39-4 SN - 978-83-62065-37-0 SN - 978-1-7281-7746-5 ER - TY - GEN A1 - Hoffmann, Javier Eduardo A1 - Brandalero, Marcelo A1 - Hübner, Michael T1 - TIRUB: A Safety and Energy-Aware Scheduling Algorithm T2 - Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), 23-25 Sept. 2020, Poznan, Poland Y1 - 2020 SN - 978-83-62065-39-4 SN - 978-83-62065-37-0 U6 - https://doi.org/10.23919/SPA50552.2020.9241280 ER - TY - GEN A1 - Veleski, Mitko A1 - Hübner, Michael A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Highly Configurable Framework for Adaptive Low Power and Error-Resilient System-On-Chip T2 - 23rd EUROMICRO Conference on Digital System Design (DSD 2020), Portoroz, Slovenia, 26 - 28 August 2020 Y1 - 2020 SN - 978-1-7281-9535-3 SN - 978-1-7281-9536-0 U6 - https://doi.org/10.1109/DSD51259.2020.00015 SP - 24 EP - 28 PB - IEEE ER - TY - GEN A1 - Medeiros, Thiarles S. A1 - Berned, Gustavo P. A1 - Navarro, Antoni A1 - Rossi, Fábio D. A1 - Luizelli, Marcelo C. A1 - Brandalero, Marcelo A1 - Hübner, Michael A1 - Beck, Antonio Carlos Schneider A1 - Lorenzon, Arthur F. T1 - Aging-Aware Parallel Execution T2 - IEEE Embedded System Letters Y1 - 2020 U6 - https://doi.org/10.1109/LES.2020.3021854 SN - 1943-0663 VL - 13 (2021) IS - 3 SP - 122 EP - 125 ER - TY - GEN A1 - Fouad, Mariam A1 - Schmitz, Georg A1 - Hübner, Michael A1 - Abdelghany, Mohamed T1 - Deep Learning in Signal Linearization for Harmonic Imaging Application T2 - IEEE 18th International Symposium on Biomedical Imaging (ISBI) Y1 - 2021 SN - 978-1-6654-1246-9 SN - 978-1-6654-1245-2 SN - 978-1-6654-2947-4 U6 - https://doi.org/10.1109/ISBI48211.2021.9434134 SN - 1945-8452 ER - TY - GEN A1 - Schmailzl, Georg J. G. A1 - Hübner, Michael T1 - From the Internet of Things to an Internet of Services in Healthcare T2 - Enhanced Telemedicine and e-Health Y1 - 2021 SN - 978-3-030-70110-9 SN - 978-3-030-70111-6 U6 - https://doi.org/10.1007/978-3-030-70111-6_7 SN - 1860-0808 SP - 141 EP - 153 ER - TY - GEN A1 - Hernandez, Hector Gerardo Muñoz A1 - Veleski, Mitko A1 - Brandalero, Marcelo A1 - Hübner, Michael ED - Derrien, Steven ED - Hannig, Frank ED - Diniz, Pedro C. ED - Chillet, Daniel T1 - Accelerating Convolutional Neural Networks in FPGA-based SoCs using a Soft-Core GPU T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications : 17th International Symposium, ARC 2021, Virtual Event, June 29–30, 2021, Proceedings Y1 - 2021 SN - 978-3-030-79024-0 SN - 978-3-030-79025-7 U6 - https://doi.org/10.1007/978-3-030-79025-7_20 SN - 0302-9743 SN - 1611-3349 SP - 275 EP - 284 PB - Springer CY - Cham ER - TY - GEN A1 - Da Silva, Bruno A. A1 - Lima, Arthur M. A1 - Garcia, Janier Arias A1 - Hübner, Michael A1 - Yudi, Jones T1 - A Manycore Vision Processor for Real-Time Smart Cameras T2 - Sensors Y1 - 2021 U6 - https://doi.org/10.3390/s21217137 SN - 1424-8220 VL - 21 IS - 21 ER - TY - GEN A1 - Rettkowski, Jens A1 - Haase, Julian A1 - Primus, Sven A1 - Hübner, Michael A1 - Göhringer, Diana T1 - Performance analysis of application-specific instruction-set routers in networks-on-chip T2 - NoCArc '21: Performance analysis of application-specific instruction-set routers in networks-on-chip Y1 - 2021 U6 - https://doi.org/10.1145/3477231.3490426 SP - 16 EP - 21 PB - ACM Digital Library CY - New York ER - TY - GEN A1 - Suawa Fogou, Priscile A1 - Meisel, Tenia A1 - Jongmanns, Marcel A1 - Hübner, Michael A1 - Reichenbach, Marc T1 - Modeling and Fault Detection of Brushless Direct Current Motor by Deep Learning Sensor Data Fusion T2 - Sensors Y1 - 2022 U6 - https://doi.org/10.3390/s22093516 SN - 1424-8220 VL - 22 IS - 9 ER - TY - GEN A1 - Hernandez, Hector Gerardo Muñoz A1 - Fricke, Florian A1 - Al Kadi, Muhammed A1 - Reichenbach, Marc A1 - Hübner, Michael T1 - Edge GPU based on an FPGA Overlay Architecture using PYNQ T2 - 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI). 2022 Y1 - 2022 SN - 978-1-6654-8128-1 SN - 978-1-6654-8129-8 U6 - https://doi.org/10.1109/SBCCI55532.2022.9893229 ER - TY - GEN A1 - Steuer, Oliver A1 - Schwarz, Daniel A1 - Oehme, Michael A1 - Schulze, J. A1 - Maczko, H. A1 - Kudrawiec, Robert A1 - Fischer, Inga Anita A1 - Heller, R. A1 - Hübner, R. A1 - Khan, M. M. A1 - Georgiev, Yordan M. A1 - Zhou, Shengqiang A1 - Helm, M. A1 - Prucnal, Slawomir T1 - Band-gap and strain engineering in GeSn alloys using post-growth pulsed laser melting T2 - Journal of Physics: Condensed Matter Y1 - 2022 U6 - https://doi.org/10.1088/1361-648X/aca3ea SN - 1361-648X VL - 35 IS - 5 ER - TY - GEN A1 - Nannipieri, Pietro A1 - Giuffrida, Gianluca A1 - Lorenzo, Diana A1 - Panicacci, Silvia A1 - Zulberti, Luca A1 - Fanucci, Luca A1 - Munoz-Hernandez, Hector Gerardo A1 - Hübner, Michael T1 - ICU4SAT: A General-Purpose Reconfigurable Instrument Control Unit Based on Open Source Components T2 - IEEE Aerospace Conference (AERO), 5-12 March 2022 Y1 - 2022 SN - 978-16654-3760-8 U6 - https://doi.org/10.1109/AERO53065.2022.9843414 SP - 1 EP - 9 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Brandalero, Marcelo A1 - Veleski, Mitko A1 - Muñoz-Hernandez, Hector Gerardo A1 - Ali, Muhammad A1 - Le Jeune, Laurens A1 - Goedemé, Toon A1 - Mentens, Nele A1 - Vandendriessche, Jurgen A1 - Lhoest, Lancelot A1 - Da Silva, Bruno A. A1 - Touhafi, Abdellah A1 - Goehringer, Diana A1 - Hübner, Michael T1 - Embedded AI Techniques for Industrial Applications T2 - 31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 30 August-3 September 2021 Y1 - 2021 SN - 978-1-6654-3759-2 U6 - https://doi.org/10.1109/FPL53798.2021.00071 SP - 374 EP - 375 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Giani, Braga A1 - Benevenuti, Fabio A1 - Gonçalves, Marcio M. A1 - Hübner, Michael A1 - Brandalero, Marcelo A1 - Kastensmidt, Fernanda A1 - Azambuja, Jose Rodrigo T1 - Evaluating softcore GPU in SRAM-based FPGA under radiation-induced effects T2 - Microelectronics Reliability Y1 - 2021 U6 - https://doi.org/10.1016/j.microrel.2021.114348 SN - 0026-2714 SN - 1872-941X VL - 126 ER - TY - GEN A1 - Gonçalves, Marcio M. A1 - Benevenuti, Fabio A1 - Munoz-Hernandez, Hector Gerardo A1 - Brandalero, Marcelo A1 - Hübner, Michael A1 - Kastensmidt, Fernanda A1 - Azambuja, Jose Rodrigo T1 - Investigating Floating-Point Implementations in a Softcore GPU under Radiation-Induced Faults T2 - 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), virtual conference, November 23-25, 2020 Y1 - 2020 SN - 978-1-7281-6044-3 SN - 978-1-7281-6045-0 U6 - https://doi.org/10.1109/ICECS49266.2020.9294939 SP - 1 EP - 4 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Brandalero, Marcelo A1 - Ali, Muhammad A1 - Le Jeune, Laurens A1 - Munoz-Hernandez, Hector Gerardo A1 - Veleski, Mitko A1 - Silva, Bruno da A1 - Lemeire, Jan A1 - Van Beeck, Kristof A1 - Touhafi, Abdellah A1 - Goedemé, Toon A1 - Mentens, Nele A1 - Göhringer, Diana A1 - Hübner, Michael T1 - AITIA: Embedded AI Techniques for Industrial Applications T2 - International Conference on Omni-Layer Intelligent Systems (COINS), 31 August-2 September 2020, Barcelona, Spain Y1 - 2020 SN - 978-1-7281-6371-0 U6 - https://doi.org/10.1109/COINS49042.2020.9191672 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Assafo, Maryam A1 - Lautsch, Martin A1 - Suawa, Priscile Fogou A1 - Jongmanns, Marcel A1 - Hübner, Michael A1 - Reichenbach, Marc A1 - Brockmann, Carsten A1 - Reinhardt, Denis A1 - Langendörfer, Peter T1 - The ForTune Toolbox: Building Solutions for Condition-Based and Predictive Maintenance Focusing on Retrofitting Y1 - 2023 SN - 978-3-8007-6204-0 SN - 978-3-8007-6203-3 N1 - Poster, Tagungsband MikroSystemTechnik Kongress 2023, Dresden, 23. - 25. Oktober 2023 SP - S. 541 PB - VDE Verlag CY - Berlin ER - TY - GEN A1 - Veleski, Mitko A1 - Hübner, Michael A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Design and implementation strategy of adaptive processor-based systems for error resilient and power-efficient operation T2 - 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS, April 7-9 2021 Y1 - 2021 SN - 978-1-6654-3595-6 U6 - https://doi.org/10.1109/DDECS52668.2021.9417023 SP - 57 EP - 62 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Veleski, Mitko A1 - Hübner, Michael A1 - Krstic, Milos A1 - Kraemer, Rolf T1 - Towards Error Resilient and Power-Efficient Adaptive Multiprocessor System using Highly Configurable and Flexible Cross-Layer Framework T2 - IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), IOLTS 2021, June 28-30, 2021 Y1 - 2021 SN - 978-1-6654-3370-9 U6 - https://doi.org/10.1109/IOLTS52814.2021.9486695 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Bielefeldt, Jens A1 - Basener, Kai-Uwe A1 - Khan, Siddique R. A1 - Massah, Mozhdeh A1 - Wiesbrock, Hans-Werner A1 - Scharoba, Stefan A1 - Hübner, Michael T1 - DeepTest: How Machine Learning Can Improve the Test of Embedded Systems  T2 - 10th Mediterranean Conference on Embedded Computing (MECO), 7-10 June 2021 Y1 - 2021 SN - 978-1-6654-3912-1 SN - 978-1-6654-2989-4 U6 - https://doi.org/10.1109/meco52532.2021.9460182 SP - 1 EP - 6 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Scharoba, Stefan A1 - Basener, Kai-Uwe A1 - Bielefeldt, Jens A1 - Wiesbrock, Hans-Werner A1 - Hübner, Michael T1 - Towards Machine Learning Support for Embedded System Tests T2 - 24th Euromicro Conference on Digital System Design, DSD 2021, virtual conference, 1-3 September 2021 Y1 - 2021 SN - 978-1-6654-2703-6 SN - 978-1-6654-2704-3 U6 - https://doi.org/10.1109/dsd53832.2021.00034 SP - 166 EP - 173 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Mahmood, Safdar A1 - Scharoba, Stefan A1 - Schorlemer, Jonas A1 - Schulz, Christian A1 - Hübner, Michael A1 - Reichenbach, Marc T1 - Detecting Improvised Land-mines using Deep Neural Networks on GPR Image Dataset targeting FPGAs  T2 - IEEE Nordic Circuits and Systems Conference (NORCAS), 25-26 October 2022, Oslo, Norway Y1 - 2022 SN - 979-8-3503-4550-6 SN - 979-8-3503-4551-3 U6 - https://doi.org/10.1109/norcas57515.2022.9934735 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Mahmood, Safdar A1 - Hübner, Michael A1 - Reichenbach, Marc ED - Palumbo, Francesca ED - Keramidas, Georgios ED - Voros, Nikolaos ED - Diniz, Pedro C. T1 - A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023 Y1 - 2023 SN - 978-3-031-42921-7 SN - 978-3-031-42920-0 U6 - https://doi.org/10.1007/978-3-031-42921-7_27 SP - 371 EP - 374 PB - Springer CY - Cham ER - TY - GEN A1 - Da Silva, Samuel Souza A1 - Cardoso, Matheus A1 - Nardo, Lucas A1 - Nepomuceno, Erivelton A1 - Hübner, Michael A1 - Arias-Garcia, Janier T1 - A New Chaos-Based PRNG Hardware Architecture Using The HUB Fixed-Point Format T2 - IEEE Transactions on Instrumentation and Measurement Y1 - 2023 U6 - https://doi.org/10.1109/TIM.2023.3235457 SN - 1557-9662 SN - 0018-9456 VL - Vol. 72 SP - 1 EP - 8 ER - TY - GEN A1 - Shahin, Keyvan A1 - Hübner, Michael A1 - Herglotz, Christian T1 - A width-configurable hardware approach for accelerating fixed-point simulation T2 - IEEE Computer Society Annual Symposium on VLSI (ISVLSI) N2 - Fixed-point simulation is a critical step in the design flow of Digital Signal Processing (DSP) systems and consumes a significant portion of the overall development time. This work proposes a novel hardware-based approach to improve the performance of fixed-point simulation through a widthconfigurable architecture implemented on Field-Programmable Gate Arrays (FPGAs). To our knowledge, this is the first reported hardware-based solution for fixed-point simulation reported in the literature, which provides substantial speedup compared to traditional software-based approaches. The presented approach utilizes High-Level Synthesis (HLS) tools to create modular, reusable components that enhance the design reusability. This approach accelerates fixed-point simulation for various applications, requiring only minor modifications to the application code to utilize it. By incorporating simulation capabilities within reusable functions, this work improves the efficiency and adaptability of the fixed-point simulation process. Implementation results for two FIR filter applications show that the proposed methodology is superior to traditional software-based approaches in reducing simulation time by two orders of magnitude and thus has the potential to improve the productivity of the DSP system design flow. KW - Fixed-Point Simulation, Width-Configurable Hardware, Hardware-based Acceleration, High-Level Synthesis (HLS) Y1 - 2025 SN - 979-8-3315-3477-6 U6 - https://doi.org/10.1109/ISVLSI65124.2025.11130205 SN - 2159-3477 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Shahin, Keyvan A1 - Hübner, Michael T1 - Accelerating fixed-point simulations using width reconfigurable hardware architectures T2 - 31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, 30 August-3 September 2021 N2 - Digital Signal Processing (DSP) systems can be described using either fixed-point or floating-point for their numeric representations. As the general computers use floating-point representation, software-based simulation tools used for modeling and simulation of the arithmetic operations in DSP systems, use floating-point representation as well. However, synthesizing customized hardware for fixed-point arithmetic operations for FPGAs or ASICs is more efficient compared to their floating-point counterparts. Thus it is necessary to convert the representation of a floating-point simulated algorithm on MATLAB for example, to a fixed-point representation which is more suitable for hardware implementation. While former approaches for this conversion step have always been software-based, like on MATLAB itself, this paper presents a new approach to show the possibility of accelerating it by using hardware width reconfigurable designs. KW - Computers, Computational modeling , Signal processing algorithms, Digital signal processing, Tools, Hardware, Numerical models Y1 - 2021 SN - 978-1-6654-3759-2 U6 - https://doi.org/10.1109/FPL53798.2021.00055 SN - 1946-1488 SP - 275 EP - 276 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Muñoz-Hernandez, Hector Gerardo A1 - Ali, Muhammad A1 - Shahin, Keyvan A1 - Siyavashi, Alireza A1 - Göhringer, Diana A1 - Reichenbach, Marc A1 - Herglotz, Christian A1 - Hübner, Michael T1 - Towards complete open-source environments : FPGA-based GPU overlay controlled by RISC-V T2 - Architecture of computing systems : 38th International Conference, ARCS 2025 Kiel, Germany, April 22–24, 2025, proceedings N2 - Image and signal processing applications have been widely implemented in Field Programmable Gate Arrays (FPGAs) and Graphical Processing Units (GPUs) due to their energy efficiency and performance, respectively. GPUs provide high data processing parallelism and are usually chosen to accelerate applications where low energy consumption is not a high priority. On the other hand, FPGAs are more tailored to hardware solutions due to their reconfigurability, but they struggle to outperform GPUs in data throughput. Soft IP cores implemented on reconfigurable hardware, are an alternative offering advantages from both worlds. Some of these soft-core solutions offer an entire environment that includes scripts to automate their implementation, custom compilers, and other diverse tools. Unfortunately, some of these soft-cores are dependent on proprietary Intellectual Property (IP) or require hardware expertise to use properly. In this work, we propose an extended version of a popular open-source soft GPU, which can now run alongside a soft RISC-V core, and with High-Bandwidth memory (HBM2) compatibility. Previously, this soft GPU was only ready to be deployed in boards with a hard ARM core, but now it can be easily used in FPGAs without this requirement. We also provide an evaluation of how the soft GPU performs with respect to the pure RISC-V core, and a hard ARM core achieving geometric mean speed-ups of 114.60x and 19.72x respectively when performing some image and signal processing applications. Finally, we demonstrate how our soft GPU benefits from the HBM integration. KW - FPGA KW - Soft-core GPU KW - System-On-Chip KW - RISC-V KW - HBM Y1 - 2025 SN - 978-3-032-03280-5 U6 - https://doi.org/https://doi.org/10.1007/978-3-032-03281-2_7 SN - 0302-9743 SP - 94 EP - 108 PB - Springer CY - Berlin ER -