TY - GEN A1 - Werner, André A1 - Fricke, Florian A1 - Shahin, Keyvan A1 - Werner, Florian A1 - Hübner, Michael ED - Hochberger, Christian ED - Nelson, Brent ED - Koch, Andreas ED - Woods, Roger ED - Diniz, Pedro C. T1 - Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms T2 - Applied Reconfigurable Computing, 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings Y1 - 2019 SN - 978-3-030-17226-8 SN - 978-3-030-17227-5 U6 - https://doi.org/0.1007/978-3-030-17227-5_20 SN - 0302-9743 SN - 1611-3349 SP - 277 EP - 291 PB - Springer CY - Cham ER - TY - GEN A1 - Korte, Jan A1 - Hübner, Michael T1 - Reactive current compensation method for PFC applications based on SOGI-PLL T2 - VLSI Circuits and Systems Letter Y1 - 2019 VL - 5 IS - 2 ER - TY - GEN A1 - Segabinazzi Ferreira, Raphael A1 - George, Nevin A1 - Chen, Junchao A1 - Hübner, Michael A1 - Krstic, Milos A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor T1 - Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness T2 - Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design N2 - Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on- line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system. Y1 - 2019 SN - 978-3-902457-54-7 U6 - https://doi.org/10.26127/BTUOpen-5050 PB - SEA-Publications CY - Kallithea, Chalkidiki (Greece) ER - TY - GEN A1 - Jenihhin, Maksim A1 - Hamdioui, Said A1 - Sonza-Reorda, Matteo A1 - Krstic, Milos A1 - Langendörfer, Peter A1 - Sauer, Christian A1 - Klotz, Anton A1 - Hübner, Michael A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor A1 - Selimis, Georgions A1 - Alexandrescu, Dan A1 - Taouil, Mottaqiallah A1 - Schrijen, Geert-Jan A1 - Sterpone, Luca A1 - Squillero, Giovanni A1 - Dyka, Zoya A1 - Raik, Jaan T1 - RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems T2 - ArXiv.org Y1 - 2019 UR - https://arxiv.org/abs/1912.01561 ER - TY - GEN A1 - Mahmood, Safdar A1 - Rettkowski, Jens A1 - Shallufa, Arij A1 - Hübner, Michael A1 - Göhringer, Diana T1 - IP Core Identification in FPGA Configuration Files using Machine Learning Techniques T2 - IEEE 9th International Conference on Consumer Electronics, Berlin, 8-11 Sept. 2019 Y1 - 2019 SN - 978-1-7281-2745-3 SN - 978-1-7281-2775-0 U6 - https://doi.org/10.1109/ICCE-Berlin47944.2019.8966236 SN - 2166-6822 SN - 2166-6814 ER - TY - GEN A1 - Rettkowski, Jens A1 - Mahmood, Safdar A1 - Shallufa, Arij A1 - Hübner, Michael A1 - Göhringer, Diana T1 - Inspection of Partial Bitstreams for FPGAs Using Artificial Neural Networks T2 - IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) Y1 - 2019 SN - 978-1-7281-3510-6 SN - 978-1-7281-3511-3 U6 - https://doi.org/10.1109/IPDPSW.2019.00023 ER - TY - GEN A1 - Fricke, Florian A1 - Werner, André A1 - Shahin, Keyvan A1 - Werner, Florian A1 - Hübner, Michael T1 - Automatic Tool-Flow for Mapping Applications to an Application-Specific CGRA Architecture T2 - IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum (IPDPSW) Y1 - 2019 SN - 978-1-7281-3510-6 SN - 978-1-7281-3511-3 U6 - https://doi.org/10.1109/IPDPSW.2019.00033 SP - 147 EP - 154 ER - TY - GEN A1 - George, Nevin A1 - Hübner, Michael A1 - Vierhaus, Heinrich Theodor T1 - From Fault Tolerance to Error Resilience: Co-Designing for Self-Awareness T2 - Proc. PhD Forum of the 9th BELAS Summer School, IHP, Frankfurt/Oder Y1 - 2019 UR - https://www.google.de/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact=8&ved=2ahUKEwjs5unQ-MvoAhWSUBUIHWVeBFIQFjABegQIAxAB&url=https%3A%2F%2Fwww.ihp-microelectronics.com%2Fdownloads%2F3616%2FBELAS19_paper_17.pdf&usg=AOvVaw2Na-b6H-YWFoZRCLRWzzYs ER - TY - GEN A1 - Fricke, Florian A1 - Hoffmann, Javier Eduardo A1 - Mahmood, Safdar A1 - Hübner, Michael T1 - A Tool to Ease De­sign-Space-Ex­plo­ra­ti­on Using the Ten­si­li­ca LX7 ASIP T2 - CDN­Li­ve EMEA 2019 KW - ASIP, LX7, Ten­si­li­ca Y1 - 2019 UR - https://www.esit.ruhr-uni-bochum.de/forschung/veroeffentlichungen/tool-ease-design-space-exploration-using-tensilica/ ER -