TY - CHAP A1 - Eric, M. A1 - Panic, Goran A1 - Stamenković, Zoran T1 - LEON2 Processor with High-Speed USB Port: A System-On-Chip for Wireless Applications Y1 - 2010 ER - TY - CHAP A1 - Marinkovic, Miroslav A1 - Piz, M. A1 - Choi, Ch.-S. A1 - Panic, Goran A1 - Ehrig, Marcus A1 - Grass, Eckhard T1 - Performance Evaluation of Channel Coding for Gbps 60-GHz OFDM-based Wireless Communications Y1 - 2010 ER - TY - GEN A1 - Panic, Goran A1 - Basmer, Thomas A1 - Tittelbach-Helmrich, Klaus A1 - Lopacinski, Lukasz T1 - Low Power Sensor Node Processor Architecture Y1 - 2010 ER - TY - CHAP A1 - Stamenković, Zoran A1 - Panic, Goran A1 - Schoof, Gunther T1 - A System-on-Chip for Wireless Body Area Sensor Network Node Y1 - 2008 ER - TY - CHAP A1 - Panic, Goran A1 - Stamenković, Zoran A1 - Kraemer, Rolf T1 - Power Gating in Wireless Sensor Networks Y1 - 2008 ER - TY - CHAP A1 - Peter, Steffen A1 - Zessack, Mario A1 - Vater, Frank A1 - Panic, Goran A1 - Frankenfeldt, Horst A1 - Methfessel, Michael T1 - An Encryption-Enabled Network Protocol Accelerator Y1 - 2008 UR - https://link.springer.com/chapter/10.1007/978-3-540-68807-5_7 ER - TY - CHAP A1 - Panic, Goran A1 - Dietterle, Daniel A1 - Stamenković, Zoran T1 - Architecture of a Power-Gated Wireless Sensor Node Y1 - 2008 ER - TY - CHAP A1 - Stamenković, Zoran A1 - Dietterle, Daniel A1 - Panic, Goran A1 - Bocer, W. A1 - Schoof, Gunther A1 - Ebert, Jean-Pierre T1 - MAC Processor for BASUMA Wireless Body Area Network Y1 - 2007 ER - TY - RPRT A1 - Dietterle, Daniel A1 - Ebert, Jean-Pierre A1 - Langendörfer, Peter A1 - Panic, Goran A1 - Peter, St. A1 - Piotrowski, Krzysztof A1 - Kersten, J. A1 - Dombrowski, Kai F. T1 - Feasibility Study Wireless Technologies for NSR applications Y1 - 2006 ER - TY - CHAP A1 - Stamenković, Zoran A1 - Panic, Goran A1 - Jagdhold, Ulrich A1 - Frankenfeldt, Horst A1 - Tittelbach-Helmrich, Klaus A1 - Schoof, Gunther A1 - Kraemer, Rolf T1 - Modular Processor: A Flexible Library of ASIC Modules Y1 - 2004 ER - TY - CHAP A1 - Panic, Goran A1 - Stamenković, Zoran A1 - Tittelbach-Helmrich, Klaus A1 - Lehmann, J. A1 - Schoof, Gunther T1 - Design of Wireless Systems Utilizing Scratchpad Memories Y1 - 2005 ER - TY - RPRT A1 - Langendörfer, Peter A1 - Piotrowski, Krzysztof A1 - Panic, Goran A1 - Sojka, A. A1 - Grilo, Antonio A1 - Barreiros d'Almeida Pereira, P. R. T1 - Specification and Testing of the Secure Middleware Architecture with an Energy Management System Y1 - 2011 ER - TY - CHAP A1 - Miletic, E. A1 - Tittelbach-Helmrich, Klaus A1 - Panic, Goran T1 - Performance Investigation on an MIMO-Capable 802.11a Compliant MAC Protocol Implementation Y1 - 2011 ER - TY - CHAP A1 - Lopacinski, Lukasz A1 - Eissa, Mohamed Hussein A1 - Panic, Goran A1 - Brzozowski, Marcin A1 - Hasani, Alireza A1 - Kraemer, Rolf T1 - Implementation of a Multi-Core Data Link Layer Processor for THz Communication T2 - IEEE 87th Vehicular Technology Conference (VTC 2018), 03 - 06 June 2018, Porto, Portugal Y1 - 2018 SN - 978-1-5386-6355-4 U6 - https://doi.org/10.1109/VTCSpring.2018.8417522 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Lopacinski, Lukasz A1 - Marinkovic, Miroslav A1 - Panic, Goran A1 - Eissa, Mohamed Hussein A1 - Hasani, Alireza A1 - Krishnegowda, Karthik A1 - Kraemer, Rolf T1 - Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology T2 - IEEE Access Y1 - 2019 U6 - https://doi.org/10.1109/ACCESS.2019.2907156 SN - 2169-3536 IS - 7 SP - 44489 EP - 44502 ER - TY - GEN A1 - Lopacinski, Lukasz A1 - Eissa, Mohamed Hussein A1 - Panic, Goran A1 - Hasani, Alireza A1 - Kraemer, Rolf T1 - Modular Data Link Layer Processing for THz Communication T2 - 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019), Cluj-Napoca, Romania, 24 - 26 April 2019 Y1 - 2019 SN - 978-1-7281-0073-9 SN - 978-1-7281-0072-2 SN - 978-1-7281-0074-6 U6 - https://doi.org/10.1109/DDECS.2019.8724657 SN - 2473-2117 SN - 2334-3133 ER - TY - GEN A1 - Panic, Goran A1 - Eissa, Mohamed Hussein A1 - Lopacinski, Lukasz A1 - Maletic, Nebojsa A1 - Kraemer, Rolf T1 - Modular Baseband Processing for mm-Wave and THz Communication T2 - Proceedings of the 8th Small Systems Simulation Symposium 2020, Niš, Serbia, 12th-14th February 2020 Y1 - 2020 UR - http://ssss.elfak.rs/wp-content/uploads/2020/02/8.pdf SP - 49 EP - 53 ER - TY - GEN A1 - Dyka, Zoya A1 - Kabin, Ievgen A1 - Brzozowski, Marcin A1 - Panic, Goran A1 - Calligaro, Cristiano A1 - Krstic, Milos A1 - Langendörfer, Peter T1 - On the SCA Resistance of Crypto IP Cores T2 - 23rd IEEE Latin-American Test Symposium (LATS 2022), Montevideo, Uruguay, 05-08 September 2022 Y1 - 2022 SN - 978-1-6654-5707-1 SN - 978-1-6654-5708-8 U6 - https://doi.org/10.1109/LATS57337.2022.9937007 SN - 2373-0862 ER - TY - GEN A1 - Dyka, Zoya A1 - Kabin, Ievgen A1 - Brzozowski, Marcin A1 - Panic, Goran A1 - Calligaro, Cristiano A1 - Krstic, Milos A1 - Langendoerfer, Peter T1 - On the influence of cell libraries and other parameters to SCA resistance of crypto IP cores T2 - 2024 13th Mediterranean Conference on Embedded Computing (MECO) N2 - The ever-growing complexity of modern systems as well as the shrinking time to market enforces the use of already designed hardware components i.e. hard and soft IP cores. The fact that also requirements with respect to security significantly increased and that side-channel analysis (SCA) attacks are meanwhile a well-known threat it is paramount to ensure SCA resistance of ASICs and FPGA implementations derived from cryptographic IP cores. This requires to evaluate this feature for each IP core and target technology even down to the level of the cell library. The experiments reported here clearly show that the three available cell libraries even though developed for the same 130nm technology of IHP exhibit different sensitivity to SCA attacks ranging from quite resistant to very vulnerable. KW - Cryptographic IP cores KW - Elliptic curve cryptography (ECC) KW - Side-channel analysis (SCA) attacks KW - SCA resistance KW - Differential power analysis (DPA) KW - Horizontal attacks Y1 - 2024 SN - 979-8-3503-8756-8 U6 - https://doi.org/10.1109/MECO62516.2024.10577776 SP - 1 EP - 5 PB - IEEE CY - Piscataway, NJ ER -