TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Perez, Eduardo A1 - Uhlmann, Max A1 - Fritscher, Markus A1 - KrishneGowda, Karthik A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator T2 - 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) N2 - The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 % and 18 %, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero. KW - RRAM Y1 - 2024 SN - 978-3-9819263-8-5 SN - 979-8-3503-4860-6 U6 - https://doi.org/10.23919/DATE58400.2024.10546709 SN - 1558-1101 SP - 1 EP - 6 PB - IEEE ER - TY - GEN A1 - Uhlmann, Max A1 - Pérez-Bosch Quesada, Emilio A1 - Fritscher, Markus A1 - Pérez, Eduardo A1 - Schubert, Markus Andreas A1 - Reichenbach, Marc A1 - Ostrovskyy, Philip A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS) N2 - The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications. KW - RRAM KW - In-Memory Computing Y1 - 2023 SN - 979-8-3503-0024-6 SN - 979-8-3503-0025-3 U6 - https://doi.org/10.1109/NEWCAS57931.2023.10198073 SN - 2474-9672 SN - 2472-467X PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Fritscher, Markus A1 - Knödtel, Johannes A1 - Mallah, Maen A1 - Pechmann, Stefan A1 - Perez-Bosch Quesada, Emilio A1 - Rizzi, Tommaso A1 - Wenger, Christian A1 - Reichenbach, Marc T1 - Mitigating the Effects of RRAM Process Variation on the Accuracy of Artifical Neural Networks T2 - Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science N2 - Weight storage is a key challenge in the efficient implementation of artificial neural networks. Novel memory technologies such as RRAM are able to greatly improve density and introduce non-volatility and multibit capabilities to this component of ANN accelerators. The usage of RRAM in this domain comes with downsides, mainly caused by cycle-to-cycle and device-to-device variability leading to erroneous readouts, greatly affecting digital systems. ANNs have the ability to compensate for this by their inherent redundancy and usually exhibit a gradual deterioration in the accuracy of the task at hand. This means, that slight error rates can be acceptable for weight storage in an ANN accelerator. In this work we link device-to-device variability to the accuracy of an ANN for such an accelerator. From this study, we can estimate how strongly a certain net is affected by a certain device parameter variability. This methodology is then used to present three mitigation strategies and to evaluate how they affect the reaction of the network to variability: a) Dropout Layers b) Fault-Aware Training c) Redundancy. These mitigations are then evaluated by their ability to improve accuracy and to lower hardware overhead by providing data for a real-word example. We improved this network’s resilience in such a way that it could tolerate double the variation in one of the device parameters (standard deviation of the oxide thickness can be 0.4 nm instead of 0.2 nm while maintaining sufficient accuracy.) KW - RRAM KW - memristive device KW - neural network Y1 - 2022 SN - 978-3-031-04579-0 SN - 978-3-031-04580-6 U6 - https://doi.org/10.1007/978-3-031-04580-6_27 SN - 0302-9743 SN - 1611-3349 SP - 401 EP - 417 PB - Springer ER - TY - CHAP A1 - Wen, Jianan A1 - Vargas, Fabian Luis A1 - Zhu, Fukun A1 - Reiser, Daniel A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Pérez, Eduardo A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Krstic, Milos T1 - Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment T2 - 2024 IEEE 25th Latin American Test Symposium (LATS) N2 - Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1109/LATS62223.2024.10534601 PB - IEEE ER - TY - GEN A1 - Jia, Ruolan A1 - Pechmann, Stefan A1 - Markus, Fritscher A1 - Wenger, Christian A1 - Zhang, Lei A1 - Hagelauer, Amelie T1 - Soft-Error Analysis of RRAM 1T1R Compute-In-Memory Core for Artificial Neural Networks T2 - 2024 39th Conference on Design of Circuits and Integrated Systems (DCIS) N2 - This work analyses SEU-induced soft-errors in analog compute-in-memory cores using resistive random-access memory (RRAM) for artificial neural networks, where their bitcells utilize one-transistor-one-RRAM (1T1R) structure. This is modeled by combining the Stanford-PKU RRAM Model and the model of the radiation-induced photocurrent in access transistors. As results, this work derives the maximal RRAM crossbar size without occurring any logic flip and indicates the requirements for RRAM technology to achieve a SEU-resilient 1T1R compute-in memory cores. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1109/DCIS62603.2024.10769203 SP - 1 EP - 5 PB - IEEE ER - TY - GEN A1 - Fritscher, Markus A1 - Singh, Simranjeet A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Reiser, Daniel A1 - Mallah, Maen A1 - Hartmann, David A1 - Bende, Ankit A1 - Kempen, Tim A1 - Uhlmann, Max A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Rana, Vikas A1 - Menzel, Stephan A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Merchant, Farhad A1 - Wenger, Christian T1 - A flexible and fast digital twin for RRAM systems applied for training resilient neural networks T2 - Scientific Reports N2 - Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT). KW - RRAM KW - Neural network KW - digital twin Y1 - 2024 U6 - https://doi.org/10.1038/s41598-024-73439-z SN - 2045-2322 VL - 14 IS - 1 PB - Springer Science and Business Media LLC ER - TY - GEN A1 - Fritscher, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - From device to application - integrating RRAM Accelerator Blocks into large AI systems T2 - 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) N2 - This work provides an introduction to design methodologies for RRAM-based systems. We illustrate the impact of device variation on the performance of neural networks and propose a circuit-level integration approach for RRAM-based compute blocks. Moreover, we demonstrate a possible architectural integration by incorporating RRAM-based VMM blocks fabricated in a 130 nm CMOS process into a RISC-V. KW - RRAM Y1 - 2024 SN - 979-8-3503-5411-9 SN - 979-8-3503-5412-6 U6 - https://doi.org/10.1109/ISVLSI61997.2024.00111 SN - 2159-3477 SP - 592 EP - 592 PB - IEEE ER - TY - GEN A1 - Fritscher, Markus A1 - Uhlmann, Max A1 - Ostrovskyy, Philip A1 - Reiser, Daniel A1 - Chen, Junchao A1 - Schubert, Andreas A1 - Schulze, Carsten A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Wenger, Christian T1 - Area-efficient digital design using RRAM-CMOS standard cells T2 - 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) N2 - Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 % smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 %. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core. KW - RRAM Y1 - 2024 SN - 979-8-3503-5411-9 SN - 979-8-3503-5412-6 U6 - https://doi.org/10.1109/ISVLSI61997.2024.00026 SN - 2159-3477 VL - 18 SP - 81 EP - 87 PB - IEEE ER - TY - GEN A1 - Vishwakarma, Abhinav A1 - Fritscher, Markus A1 - Hagelauer, Amelie A1 - Reichenbach, Marc T1 - An RRAM-based building block for reprogrammable non-uniform sampling ADCs T2 - Information Technology : it Y1 - 2023 U6 - https://doi.org/10.1515/itit-2023-0021 SN - 2196-7032 VL - 65 IS - 1-2 SP - 39 EP - 51 ER - TY - GEN A1 - Reiser, Daniel A1 - Reichenbach, Marc A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Wenger, Christian A1 - Zambelli, Cristian A1 - Bertozzi, Davide T1 - Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom N2 - In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate multi-level conductance operation. The support of drift models in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they overlook key device- and array-level parameters affecting drift resilience such as the programming algorithm of RRAM cells, the choice of target conductance states and the weight-toconductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability. KW - RRAM Y1 - 2023 SN - 979-8-3503-0024-6 SN - 979-8-3503-0025-3 U6 - https://doi.org/10.1109/NEWCAS57931.2023 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Wen, Jianan A1 - Vargas, Fabian Luis A1 - Zhu, Fukun A1 - Reiser, Daniel A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Perez, Eduardo A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Krstic, Milos T1 - RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation T2 - Microelectronics Reliability N2 - The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current–voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector–matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments. KW - RRAM Y1 - 2025 U6 - https://doi.org/10.1016/j.microrel.2025.115630 SN - 0026-2714 VL - 168 SP - 1 EP - 10 PB - Elsevier BV CY - Amsterdam ER - TY - GEN A1 - Spetzler, Benjamin A1 - Fritscher, Markus A1 - Park, Seongae A1 - Kim, Nayoun A1 - Wenger, Christian A1 - Ziegler, Martin T1 - AI-driven model for optimized pulse programming of memristive devices T2 - APL Machine Learning N2 - Next-generation artificial intelligence (AI) hardware based on memristive devices offers a promising approach to reducing the increasingly large energy consumption of AI applications. However, programming memristive AI hardware to achieve a desired synaptic weight configuration remains challenging because it requires accurate and energy-efficient algorithms for selecting the optimal weight-update pulses. Here, we present a computationally efficient AI model for predicting the weight update of memristive devices and guiding device programming. The synaptic weight-update behavior of bilayer HfO2/TiO2 memristive devices is characterized over a range of pulse parameters to provide experimental data for the AI model. Three different artificial neural network (ANN) configurations are trained and evaluated regarding the amount of training data required for accurate predictions and the computational costs. Finally, we apply the model to an antipulse weight-update process to demonstrate its performance. The results show that accurate and computationally inexpensive predictions are possible with comparatively few datasets and small ANNs. The normalized weight-update processes are predicted with accuracies comparable with larger model architectures but require only 896 floating point operations and 8.33 nJ per inference. This makes the model a promising candidate for integration into AI-driven device controllers as a precise and energy-efficient solution for memristive device programming. KW - RRAM KW - Neural network KW - Device model Y1 - 2025 U6 - https://doi.org/10.1063/5.0251113 SN - 2770-9019 VL - 3 IS - 2 SP - 1 EP - 7 PB - AIP Publishing ER - TY - GEN A1 - Fritscher, Markus A1 - Uhlmann, Max A1 - Ostrovskyy, Philip A1 - Reiser, Daniel A1 - Chen, Junchao A1 - Wen, Jianan A1 - Schulze, Carsten A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Wenger, Christian ED - Wenger, Christian T1 - RISC-V CPU design using RRAM-CMOS standard cells T2 - IEEE transactions on very large scale integration (VLSI) systems N2 - The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates. KW - RRAM KW - Logic gates Y1 - 2025 UR - https://ieeexplore.ieee.org/document/10960690 U6 - https://doi.org/10.1109/TVLSI.2025.3554476 SN - 1063-8210 SP - 1 EP - 9 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER - TY - GEN A1 - Aftowicz, Marcin A1 - Fritscher, Markus A1 - Lehniger, Kai A1 - Wenger, Christian A1 - Langendörfer, Peter A1 - Brzozowski, Marcin T1 - Hardware-friendly Nyström approximation for water treatment anomaly detection T2 - IECON 2024 - 50th Annual Conference of the IEEE Industrial Electronics Society : proceedings N2 - This paper presents an approach to accelerate One-Class Support Vector Machines (SVM) using a hardware-friendly kernel that doesn't rely on multiplication operations, thus adaptable to hardware platforms. Leveraging Nyström approximation, we implemented a pipeline and compared its performance against a software implementation using libsvm. Furthermore, we evaluated the efficiency of our approach by deploying it on an FPGA. Our experiments, conducted on the SWaT dataset, demonstrate a 50x speedup using the FPGA implementation, achieving a classification time of 21 microseconds per instance. Importantly, we find no degradation in performance, as measured by the f-score of the attack class in the test set. This study explores the potential of hardware acceleration in optimizing anomaly detection systems for real-time applications. KW - OCSVM KW - FPGA KW - Nyström KW - Anomaly Detection KW - SWaT Y1 - 2024 SN - 978-1-6654-6454-3 U6 - https://doi.org/10.1109/IECON55916.2024.10905880 SP - 1 EP - 7 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - Piscataway, NJ ER -