TY - GEN A1 - Kaletta, Udo Christian A1 - Wipf, Christian A1 - Fraschke, Mirko A1 - Wolansky, Dirk A1 - Schubert, Markus Andreas A1 - Schroeder, Thomas A1 - Wenger, Christian T1 - AlN/SiO2/Si3N4/Si(100) based CMOS compatible surface acoustic wave filter with -12.8 dB minimum insertion loss T2 - IEEE Transactions on Electron Devices Y1 - 2015 U6 - https://doi.org/10.1109/TED.2015.2395443 SN - 0018-9383 VL - 62 IS - 3 SP - 764 EP - 768 ER - TY - GEN A1 - Niu, Gang A1 - Calka, Pauline A1 - Walczyk, Christian A1 - Guha, Subhajit A1 - Fraschke, Mirko A1 - Fröhlich, K. A1 - Hamoumou, Philippe A1 - Gautier, Brice A1 - Alff, Lambert A1 - Schröder, Thomas T1 - Geometric conductive filament confinement by nanotips for resistive switching of HfO₂-RAM devices with high performance T2 - Scientific Reports Y1 - 2016 SN - 2045-2322 VL - 6 IS - 25757 ER - TY - GEN A1 - Dorai Swamy Reddy, Keerthi A1 - Pérez, Eduardo A1 - Baroni, Andrea A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Marschmeyer, Steffen A1 - Fraschke, Mirko A1 - Lisker, Marco A1 - Wenger, Christian A1 - Mai, Andreas T1 - Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance T2 - The European Physical Journal B N2 - Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1140/epjb/s10051-024-00821-1 SN - 1434-6028 VL - 97 PB - Springer Science and Business Media LLC ER -