TY - GEN A1 - Fricke, Florian A1 - Werner, André A1 - Shahin, Keyvan A1 - Werner, Florian A1 - Hübner, Michael T1 - Automatic Tool-Flow for Mapping Applications to an Application-Specific CGRA Architecture T2 - IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum (IPDPSW) Y1 - 2019 SN - 978-1-7281-3510-6 SN - 978-1-7281-3511-3 U6 - https://doi.org/10.1109/IPDPSW.2019.00033 SP - 147 EP - 154 ER - TY - GEN A1 - Werner, André A1 - Fricke, Florian A1 - Shahin, Keyvan A1 - Werner, Florian A1 - Hübner, Michael ED - Hochberger, Christian ED - Nelson, Brent ED - Koch, Andreas ED - Woods, Roger ED - Diniz, Pedro C. T1 - Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms T2 - Applied Reconfigurable Computing, 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings Y1 - 2019 SN - 978-3-030-17226-8 SN - 978-3-030-17227-5 U6 - https://doi.org/0.1007/978-3-030-17227-5_20 SN - 0302-9743 SN - 1611-3349 SP - 277 EP - 291 PB - Springer CY - Cham ER - TY - GEN A1 - Fricke, Florian A1 - Scharoba, Stefan A1 - Rachuj, Sebastian A1 - Konopik, Andreas A1 - Kluge, Florian A1 - Hofstetter, Georg A1 - Reichenbach, Marc ED - Orailoglu, Alex ED - Reichenbach, Marc ED - Jung, Matthias T1 - Application Runtime Estimation for AURIX Embedded MCU Using Deep Learning  T2 - Embedded computer systems : architectures, modeling, and simulation : 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, proceedings Y1 - 2022 SN - 978-3-031-15073-9 SN - 978-3-031-15074-6 U6 - https://doi.org/10.1007/978-3-031-15074-6_15 SP - 235 EP - 249 PB - Springer CY - Cham ER - TY - GEN A1 - Fricke, Florian A1 - Hoffmann, Javier Eduardo A1 - Mahmood, Safdar A1 - Hübner, Michael T1 - A Tool to Ease De­sign-Space-Ex­plo­ra­ti­on Using the Ten­si­li­ca LX7 ASIP T2 - CDN­Li­ve EMEA 2019 KW - ASIP, LX7, Ten­si­li­ca Y1 - 2019 UR - https://www.esit.ruhr-uni-bochum.de/forschung/veroeffentlichungen/tool-ease-design-space-exploration-using-tensilica/ ER - TY - GEN A1 - Fricke, Florian A1 - Mahmood, Safdar A1 - Hoffmann, Javier Eduardo A1 - Ali, Muhammad A1 - Shahin, Keyvan A1 - Hübner, Michael A1 - Göhringer, Diana T1 - Domain Adaptive Processor Architectures T2 - Kommunikation und Bildverarbeitung in der Automation Y1 - 2020 SN - 978-3-662-59895-5 SN - 978-3-662-59894-8 U6 - https://doi.org/10.1007/978-3-662-59895-5_23 SN - 2522-8579 SN - 2522-8587 SP - 315 EP - 330 ER - TY - CHAP A1 - Mori Alves da Silva, Jones Yudi A1 - Werner, André A1 - Shallufa, Arij A1 - Fricke, Florian A1 - Hübner, Michael T1 - A Design Methodology for the Next Generation Real-Time Vision Processors T2 - Applied reconfigurable computing, 12th international symposium, ARC 2016, Mangaratiba, RJ, Brazil, March 22-24, 2016 Y1 - 2016 SN - 978-3-319-30480-9 SN - 978-3-319-30481-6 SP - 14 EP - 25 PB - Springer CY - Cham ER - TY - CHAP A1 - Mori Alves da Silva, Jones Yudi A1 - Werner, André A1 - Fricke, Florian A1 - Hübner, Michael T1 - A rapid prototyping method to reduce the design time in commercial high-level synthesis tools T2 - 23rd Re­con­fi­gura­ble Ar­chi­tec­tu­res Work­shop (RAW 2016), Chi­ca­go, USA Y1 - 2016 SN - 978-1-5090-3682-0 SP - 253 EP - 258 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Fricke, Florian A1 - Werner, André A1 - Hübner, Michael T1 - Tool flow for automatic generation of architectures and test-cases to enable the evaluati-on of CGRAs in the context of HPC applications T2 - Conference on Design and Architectures for Signal and Image Processing (DASIP), 27-29 Sept. 2017, Dresden, Germany Y1 - 2017 UR - https://ieeexplore.ieee.org/document/8122124 SN - 978-1-5386-3534-6 U6 - https://doi.org/10.1109/DASIP.2017.8122124 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Fricke, Florian A1 - Werner, André A1 - Janßen, Benedikt A1 - Hübner, Michael A1 - Ribbe, Clemens A1 - Cengizhan, Inac T1 - Redesign of an Educational Robot Platform Using Web-based Programming T2 - Proceedings of the 2016 Workshop on Embedded and Cyber-Physical Systems Education, Pittsburgh, PA, USA - October 01-07, 2016 Y1 - 2016 SN - 978-1-4503-4657-3 U6 - https://doi.org/10.1145/3005329.3005332 PB - ACM CY - New York, NY ER - TY - CHAP A1 - Fricke, Florian A1 - Werner, André A1 - Shahin, Keyvan A1 - Hübner, Michael ED - Voros, Nikolaos ED - Hübner, Michael ED - Keramidas, Georgios ED - Göhringer, Diana ED - Antonopoulos, Christos ED - Diniz, Pedro C. T1 - CGRA Tool Flow for Fast Run-Time Reconfiguration T2 - Proceedings, 14th International Symposium on Applied Reconfigurable Computing, Santorini, Greece, May 2-4, 2018 Y1 - 2018 SN - 978-3-319-78889-0 SN - 978-3-319-78890-6 U6 - https://doi.org/10.1007/978-3-319-78890-6_53 SP - 661 EP - 672 PB - Springer CY - Cham ER - TY - GEN A1 - Fricke, Florian A1 - Brandalero, Marcelo A1 - Liehr, Sascha A1 - Kern, Simon A1 - Meyer, Klas A1 - Kowarik, Stefan A1 - Hierzegger, Robin A1 - Westerdick, Stephan A1 - Maiwald, Michael A1 - Hübner, Michael T1 - Artificial Intelligence for Mass Spectrometry and Nuclear Magnetic Resonance Spectroscopy Using a Novel Data Augmentation Method T2 - IEEE Transactions on Emerging Topics in Computing Y1 - 2022 U6 - https://doi.org/10.1109/TETC.2021.3131371 SN - 2168-6750 VL - 10 IS - 1 SP - 87 EP - 98 ER - TY - GEN A1 - Hernandez, Hector Gerardo Muñoz A1 - Fricke, Florian A1 - Al Kadi, Muhammed A1 - Reichenbach, Marc A1 - Hübner, Michael T1 - Edge GPU based on an FPGA Overlay Architecture using PYNQ T2 - 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI). 2022 Y1 - 2022 SN - 978-1-6654-8128-1 SN - 978-1-6654-8129-8 U6 - https://doi.org/10.1109/SBCCI55532.2022.9893229 ER -