TY - CHAP A1 - Pashmineh, Sara A1 - Killat, Dirk T1 - A high-voltage driver based on stacked low-voltage transistors with minimized on-resistance for a buck converter in 65 nm CMOS T2 - 2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), 15-18 May 2016 N2 - This paper presents a high-voltage (HV) driver for switching a buck converter. The circuit is based on 3-stacked CMOS using gate control circuits to drive maximum current which indicates minimized on-resistance of the HV-driver thus achieving faster switching. The circuit is designed and fabricated using 65 nm CMOS TSMC process technology with a nominal voltage of 2.5 V and with a supply voltage of 5.5 V. Since the design is based on stacked CMOS transistors, the circuit is technology-independent. The initial on-resistances of the driver pull-up and the pull-down paths have an improvement of 75% and 36% respectively. Due to a buck converter switched by the designed HV-driver, output voltages in the range of 0.45 V to 2.45 V can be achieved from different high supply voltages in the range of 3.5 V to 5.5 V. The circuit occupies an area of 0.187 mm2. Y1 - 2016 UR - http://ieeexplore.ieee.org/document/7726692/ SN - 978-1-4673-8721-7 SN - 978-1-4673-8722-4 U6 - https://doi.org/10.1109/CCECE.2016.7726692 SP - 1 EP - 5 PB - IEEE CY - Piscataway, NJ ER - TY - CHAP A1 - Pashmineh, Sara A1 - Killat, Dirk A1 - Bramburger, Stefan T1 - Design of a high-voltage rail-to-rail error amplifier based on standard CMOS used in an LDO T2 - 2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE, 15-18 May 2016 N2 - This paper presents the design of a high-voltage (HV) rail-to-rail error amplifier. This circuit controls the output signal of a low drop-out voltage regulator (LDO) according to the reference voltages and based on stacked standard transistors. The circuit is designed using 65 nm CMOS process technology with a nominal voltage of 2.5 V and is optimized for arbitrary values of supply voltage up to 5.0 V. The error amplifier consists of 3 stages and 2 feedback loops. The stages are internally connected rail-to-rail to achieve high GBW and DC accuracy. The simulation and measurement results for the designed HV-error amplifier show that the output signal of the LDO tracks the reference voltages. The circuit design is technology-independent and compatible with scaled CMOS. Y1 - 2016 UR - http://ieeexplore.ieee.org/document/7726693/ SN - 978-1-4673-8721-7 SN - 978-1-4673-8722-4 U6 - https://doi.org/10.1109/CCECE.2016.7726693 SP - 1 EP - 5 PB - IEEE CY - Piscataway, NJ ER -