TY - THES A1 - Beyer, Dirk T1 - Formale Verifikation von Realzeit-Systemen mittels Cottbus Timed Automata KW - Formal Verification KW - Formal Method KW - Timed Automata KW - Reachability Analysis KW - BDD KW - Reactive Systems KW - Embedded Systems KW - Protocol Verification Y1 - 2002 U6 - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:kobv:co1-000000258 UR - http://opus.kobv.de/btu/volltexte/2007/55/ ER -