TY - GEN A1 - Pérez, Eduardo A1 - Maldonado, David A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Perez-Bosch Quesada, Emilio A1 - Cantudo, Antonio A1 - Jimenez-Molinos, Francisco A1 - Wenger, Christian A1 - Roldan, Juan Bautista T1 - A comparison of resistive switching parameters for memristive devices with HfO2 monolayers and Al2O3/HfO2 bilayers at the wafer scale T2 - 14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023 N2 - Memristive devices integrated in 200 mm wafers manufactured in 130 nm CMOS technology with two different dielectrics, namely, a HfO2 monolayer and an Al2O3/HfO2 bilayer, have been measured. The cycle-to-cycle (C2C) and device-todevice (D2D) variability have been analyzed at the wafer scale using different numerical methods to extract the set (Vset) and reset (Vreset) voltages. Some interesting differences between both technologies were found in terms of switching characteristics KW - RRAM Y1 - 2023 SN - 979-8-3503-0240-0 U6 - https://doi.org/10.1109/CDE58627.2023.10339417 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Reiser, Daniel A1 - Reichenbach, Marc A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Wenger, Christian A1 - Zambelli, Cristian A1 - Bertozzi, Davide T1 - Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom N2 - In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate multi-level conductance operation. The support of drift models in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they overlook key device- and array-level parameters affecting drift resilience such as the programming algorithm of RRAM cells, the choice of target conductance states and the weight-toconductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability. KW - RRAM Y1 - 2023 SN - 979-8-3503-0024-6 SN - 979-8-3503-0025-3 U6 - https://doi.org/10.1109/NEWCAS57931.2023 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Franck, Max A1 - Dabrowski, Jarek A1 - Schubert, Markus Andreas A1 - Vignaud, Dominique A1 - Achehboune, Mohamed A1 - Colomer, Jean‐François A1 - Henrard, Luc A1 - Wenger, Christian A1 - Lukosius, Mindaugas T1 - Investigating Impacts of Local Pressure and Temperature on CVD Growth of Hexagonal Boron Nitride on Ge(001)/Si T2 - Advanced Materials Interfaces N2 - AbstractThe chemical vapor deposition (CVD) growth of hexagonal boron nitride (hBN) on Ge substrates is a promising pathway to high‐quality hBN thin films without metal contaminations for microelectronic applications, but the effect of CVD process parameters on the hBN properties is not well understood yet. The influence of local changes in pressure and temperature due to different reactor configurations on the structure and quality of hBN films grown on Ge(001)/Si is studied. Injection of the borazine precursor close to the sample surface results in an inhomogeneous film thickness, attributed to an inhomogeneous pressure distribution at the surface, as shown by computational fluid dynamics simulations. The additional formation of nanocrystalline islands is attributed to unfavorable gas phase reactions due to the radiative heating of the injector. Both issues are mitigated by increasing the injector‐sample distance, leading to an 86% reduction in pressure variability on the sample surface and a 200 °C reduction in precursor temperature. The resulting hBN films exhibit no nanocrystalline islands, improved thickness homogeneity, and high crystalline quality (Raman FWHM = 23 cm−1). This is competitive with hBN films grown on other non‐metal substrates but achieved at lower temperature and with a low thickness of only a few nanometers. KW - Boron Nitride KW - 2D material Y1 - 2025 U6 - https://doi.org/10.1002/admi.202400467 SN - 2196-7350 VL - 12 IS - 1 PB - Wiley ER - TY - GEN A1 - Wen, Jianan A1 - Vargas, Fabian Luis A1 - Zhu, Fukun A1 - Reiser, Daniel A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Perez, Eduardo A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Krstic, Milos T1 - RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation T2 - Microelectronics Reliability N2 - The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current–voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector–matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments. KW - RRAM Y1 - 2025 U6 - https://doi.org/10.1016/j.microrel.2025.115630 SN - 0026-2714 VL - 168 SP - 1 EP - 10 PB - Elsevier BV CY - Amsterdam ER - TY - GEN A1 - Spetzler, Benjamin A1 - Fritscher, Markus A1 - Park, Seongae A1 - Kim, Nayoun A1 - Wenger, Christian A1 - Ziegler, Martin T1 - AI-driven model for optimized pulse programming of memristive devices T2 - APL Machine Learning N2 - Next-generation artificial intelligence (AI) hardware based on memristive devices offers a promising approach to reducing the increasingly large energy consumption of AI applications. However, programming memristive AI hardware to achieve a desired synaptic weight configuration remains challenging because it requires accurate and energy-efficient algorithms for selecting the optimal weight-update pulses. Here, we present a computationally efficient AI model for predicting the weight update of memristive devices and guiding device programming. The synaptic weight-update behavior of bilayer HfO2/TiO2 memristive devices is characterized over a range of pulse parameters to provide experimental data for the AI model. Three different artificial neural network (ANN) configurations are trained and evaluated regarding the amount of training data required for accurate predictions and the computational costs. Finally, we apply the model to an antipulse weight-update process to demonstrate its performance. The results show that accurate and computationally inexpensive predictions are possible with comparatively few datasets and small ANNs. The normalized weight-update processes are predicted with accuracies comparable with larger model architectures but require only 896 floating point operations and 8.33 nJ per inference. This makes the model a promising candidate for integration into AI-driven device controllers as a precise and energy-efficient solution for memristive device programming. KW - RRAM KW - Neural network KW - Device model Y1 - 2025 U6 - https://doi.org/10.1063/5.0251113 SN - 2770-9019 VL - 3 IS - 2 SP - 1 EP - 7 PB - AIP Publishing ER - TY - GEN A1 - Fritscher, Markus A1 - Uhlmann, Max A1 - Ostrovskyy, Philip A1 - Reiser, Daniel A1 - Chen, Junchao A1 - Wen, Jianan A1 - Schulze, Carsten A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Wenger, Christian ED - Wenger, Christian T1 - RISC-V CPU design using RRAM-CMOS standard cells T2 - IEEE transactions on very large scale integration (VLSI) systems N2 - The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7% smaller area than the equivalent design using standard CMOS gates. KW - RRAM KW - Logic gates Y1 - 2025 UR - https://ieeexplore.ieee.org/document/10960690 U6 - https://doi.org/10.1109/TVLSI.2025.3554476 SN - 1063-8210 SP - 1 EP - 9 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER - TY - GEN A1 - Strobel, Carsten A1 - Chavarin, Carlos A. A1 - Knaut, Martin A1 - Wenger, Christian A1 - Heinzig, André A1 - Mikolajick, Thomas T1 - Demonstration of a graphene adjustable‐barriers phototransistor with tunable ultra‐high responsivity T2 - Advanced Optical Materials N2 - The development of high‐speed dual‐band photodetectors with high responsivity is important for several applications such as optical communication, biomedical imaging or spectroscopy. In this work, a phototransistor with ultra‐high responsivity is demonstrated, which potentially also allows for very high bandwidths. The device is called graphene adjustable‐barriers phototransistor and is potentially capable for dual‐band detection in the visible‐infrared (VIS‐IR) range. A material combination of intrinsic hydrogenated amorphous silicon, graphene, and n‐type germanium (n‐Ge) is used for the demonstrator. The device operation is based on the light induced modulation of the graphene Fermi energy level and Schottky barrier heights. For the first time, the functional mechanism of the device is successfully demonstrated in the VIS range with responsivities exceeding 107 A/W at a gate voltage of 20V. The bandwidth of the device is 1.2 kHz and is so far limited by the defective gate material hydrogenated amorphous silicon and relaxed feature sizes of the demonstrator. These results are an important step toward a new generation of high‐responsivity high‐speed photo detection devices. KW - Graphene KW - Detector Y1 - 2025 U6 - https://doi.org/10.1002/adom.202500344 SN - 2195-1071 SP - 1 EP - 9 PB - Wiley-VCH GmbH CY - Weinheim ER - TY - GEN A1 - Morales, Carlos A1 - Gertig, Max A1 - Kot, Małgorzata A1 - Alvarado, Carlos A1 - Schubert, Markus Andreas A1 - Zoellner, Marvin Hartwig A1 - Wenger, Christian A1 - Henkel, Karsten A1 - Flege, Jan Ingo T1 - In situ X‐ray photoelectron spectroscopy study of atomic layer deposited cerium oxide on SiO₂ : substrate influence on the reaction mechanism during the early stages of growth T2 - Advanced materials interfaces N2 - Thermal atomic layer deposition (ALD) of cerium oxide using commercial Ce(thd)4 precursor and O3 on SiO2 substrates is studied employing in‐situ X‐ray photoelectron spectroscopy (XPS). The system presents a complex growth behavior determined by the change in the reaction mechanism when the precursor interacts with the substrate or the cerium oxide surface. During the first growth stage, non‐ALD side reactions promoted by the substrate affect the growth per cycle, the amount of carbon residue on the surface, and the oxidation degree of cerium oxide. On the contrary, the second growth stage is characterized by a constant growth per cycle in good agreement with the literature, low carbon residues, and almost fully oxidized cerium oxide films. This distinction between two growth regimes is not unique to the CeOx/SiO2 system but can be generalized to other metal oxide substrates. Furthermore, the film growth deviates from the ideal layer‐by‐layer mode, forming micrometric inhomogeneous and defective flakes that eventually coalesce for deposit thicknesses above 10 nm. The ALD‐cerium oxide films present less order and a higher density of defects than films grown by physical vapor deposition techniques, likely affecting their reactivity in oxidizing and reducing conditions. KW - Atomic Layer Deposition (ALD) KW - Cerium oxide KW - In-situ X-ray Photoelectron spectroscopy (in-situ XPS) KW - Growth model KW - Substrate influence Y1 - 2025 U6 - https://doi.org/10.1002/admi.202400537 SN - 2196-7350 VL - 12 IS - 5 SP - 1 EP - 13 PB - Wiley CY - Weinheim ER - TY - GEN A1 - Maldonado, D. A1 - Acal, C. A1 - Ortiz, H. A1 - Aguilera, A.M. A1 - Ruiz-Castro, J.E. A1 - Cantudo, A. A1 - Baroni, A. A1 - Dorai Swamy Reddy, K. A1 - Pechmann, S. A1 - Uhlmann, M. A1 - Wenger, Christian A1 - Pérez, E. A1 - Roldán, J.B. T1 - A comprehensive statistical study of the post-programming conductance drift in HfO2-based memristive devices T2 - Materials science in semiconductor processing N2 - The conductance drift in HfO2-based memristors is a critical reliability concern that impacts in their application in non-volatile memory and neuromorphic computing integrated circuits. In this work we present a comprehensive statistical analysis of the conductance drift behavior in resistive random access memories (RRAM) whose physics is based on valence change mechanisms. We experimentally characterize the conductance time evolution in six different resistance states and analyze the suitability of various probability distributions to model the observed variability. Our results reveal that the log-logistic probability distribution provides the best fit to the experimental data for the resistance multilevels and the measured post-programming times under consideration. Additionally, we employ an analysis of variance (ANOVA) to statistically analyze the post-programming time and current level effects on the observed variability. Finally, in the context of the Stanford compact model, we describe how variability has to be implemented to obtain the probability distribution of measured current values. KW - RRAM KW - Neural network KW - Variability Y1 - 2025 U6 - https://doi.org/10.1016/j.mssp.2025.109668 SN - 1369-8001 VL - 196 SP - 1 EP - 8 PB - Elsevier BV CY - Amsterdam ER - TY - GEN A1 - Raju, Ashraful Islam A1 - Dubey, Pawan Kumar A1 - Lukose, Rasuole A1 - Wenger, Christian A1 - Mai, Andreas A1 - Lukosius, Mindaugas T1 - Optimized silicon nitride-spaced graphene electro-optic modulator with high efficiency and bandwidth T2 - Optical and quantum electronics N2 - Optical modulators with high modulation efficiency, large operational bandwidth, high-speed and low energy consumption is essential for the advancement of on-chip optical signal processing. To overcome the bandwidth-efficiency trade-off in graphene optical modulators, a buried silicon nitride waveguide-coupled double-layer graphene electro-absorption (EA) optical modulator has been proposed. In the proposed design, silicon nitride layer is also embedded between the two graphene layers as a dielectric spacer to enhance the graphene-light interaction. An extensive simulation has been performed to optimize the dielectric spacing layers between the two graphene for optimal device performance including the waveguide dimensions and optical modes profile. The simulated results show a high modulation efficiency of 1.1 dB/V and a modulation depth of 0.16 dB/µm, corresponding to a 15-dB extinction ratio for a 100 µm device at 1550 nm, with a 30 nm spacer and 12 V driving voltage. The proposed modulator achieves a 14 GHz bandwidth and operates over a 1050 nm broadband operation spectral range. The concurrent presence of high modulation bandwidth and efficiency renders these modulator designs highly viable for on-chip optical communication applications. KW - Graphene KW - Modulator Y1 - 2025 U6 - https://doi.org/10.1007/s11082-025-08310-0 SN - 1572-817X VL - 57 IS - 7 SP - 1 EP - 15 PB - Springer Science and Business Media LLC CY - Dordrecht ER - TY - GEN A1 - Morales, Carlos A1 - Tschammer, Rudi A1 - Pożarowska, Emilia A1 - Kosto, Julia A1 - Villar‐Garcia, Ignacio J. A1 - Pérez‐Dieste, Virginia A1 - Favaro, Marco A1 - Starr, David E. A1 - Kapuścik, Paulina A1 - Mazur, Michał A1 - Wojcieszak, Damian A1 - Domaradzki, Jarosław A1 - Alvarado, Carlos A1 - Wenger, Christian A1 - Henkel, Karsten A1 - Flege, Jan Ingo T1 - Hydrogen sensing via heterolytic H₂ activation at room temperature by atomic layer deposited ceria T2 - ChemSusChem : chemistry, sustainability, energy, materials N2 - Ultrathin atomic layer deposited ceria films (<20 nm) are capable of H2 heterolytic activation at room temperature, undergoing a significant reduction regardless of the absolute pressure, as measured under in‐situ conditions by near ambient pressure X‐ray photoelectron spectroscopy. ALD‐ceria can gradually reduce as a function of H2 concentration under H2/O2 environments, especially for diluted mixtures below 10 %. At room temperature, this reduction is limited to the surface region, where the hydroxylation of the ceria surface induces a charge transfer towards the ceria matrix, reducing Ce4+ cations to Ce3+. Thus, ALD‐ceria replicates the expected sensing mechanism of metal oxides at low temperatures without using any noble metal decorating the oxide surface to enhance H2 dissociation. The intrinsic defects of the ALD deposit seem to play a crucial role since the post‐annealing process capable of healing these defects leads to decreased film reactivity. The sensing behavior was successfully demonstrated in sensor test structures by resistance changes towards low concentrations of H2 at low operating temperatures without using noble metals. These promising results call for combining ALD‐ceria with more conductive metal oxides, taking advantage of the charge transfer at the interface and thus modifying the depletion layer formed at the heterojunction. KW - Atomic Layer Deposition KW - Ceria KW - Hydrogen Sensing KW - X-Ray photoelectron spectroscopy KW - Raman spectroscopy KW - Resitive sensor Y1 - 2025 U6 - https://doi.org/10.1002/cssc.202402342 SN - 1864-5631 VL - 18 IS - 13 SP - 1 EP - 13 PB - Wiley-VCH CY - Weinheim ER - TY - GEN A1 - Fünning, Tabea A1 - Paul, Martin A1 - Manganelli, Costanza Lucia A1 - Wenger, Christian A1 - Mai, Andreas A1 - Steglich, Patrick T1 - Comparative simulation analysis of photonic ultrasound sensors based on silicon waveguides T2 - Scientific reports N2 - Pressure sensors based on photonic integrated circuits (PIC) offer the prospect of outstanding sensitivities, extreme miniaturization and have the potential for highly scalable production using CMOS compatible processing. PIC-based pressure sensors detect the change in optical properties, i.e. the intensity or phase of the optical carrier wave inside miniaturized waveguide structures. The detection of ultrasound is achieved by engineering the waveguide architecture such that a pressure causes a high change in the effective refractive index of the waveguide. A range of PIC-based pressure sensors have been reported, but a comparison of the sensitivity of the different approaches is not straightforward, since different pressure sensitive waveguide architectures as well as photonic layouts and measurement setups impact the performance. Additionally, the used sensitivity unit is not uniform throughout the different studies, further complicating a comparison. In this work, a detailed simulation study is carried out by finite element modeling of different pressure sensitive waveguide architectures for a consistent comparison. We analyze three different sensor architectures: (A) a free standing membrane located within a tiny air gap above the waveguide, (B) a waveguide located on top of a deflectable membrane as well as (C) a waveguide embedded inside a pressure-sensitive polymer cladding. The mechanical response of the structures and the resulting changes in mode propagation, i.e. the change of the effective refractive index, are analyzed. The waveguide sensitivities in RIU/MPa for different waveguide types (strip, slot) and polarization states (TE, TM) are compared. The results reveal inherent limitations of the different waveguide designs and create a basis for the selection of suitable designs for further ultrasound sensor development. Possibilities for enhancing waveguide sensitivity are identified and discussed. Additionally, we have shown that the studied approaches are extensible to SiN waveguides. KW - Ultrasound sensor Y1 - 2025 U6 - https://doi.org/10.1038/s41598-025-01953-9 SN - 2045-2322 VL - 15 IS - 1 SP - 1 EP - 13 PB - Springer Science and Business Media LLC CY - [London] ER - TY - GEN A1 - Uhlmann, Max A1 - Krysik, Milosz A1 - Wen, Jianan A1 - Frohberg, Max A1 - Baroni, Andrea A1 - Reddy, Keerthi Dorai Swamy A1 - Pérez, Eduardo A1 - Ostrovskyy, Philip A1 - Piotrowski, Krzysztof A1 - Carta, Corrado A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - A compact one-transistor-multiple-RRAM characterization platform T2 - IEEE transactions on circuits and systems I : regular papers N2 - Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP’s 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 %. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells. KW - RRAM KW - Vector Matrix Multiplication Y1 - 2025 U6 - https://doi.org/10.1109/TCSI.2025.3555234 SN - 1549-8328 SP - 1 EP - 12 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER -