TY - GEN
A1 - Nitsch, Paul-G.
A1 - Ratzke, Markus
A1 - Pozarowska, Emilia
A1 - Flege, Jan Ingo
A1 - Alvarado Chavarin, Carlos
A1 - Wenger, Christian
A1 - Fischer, Inga Anita
T1 - Deposition of reduced ceria thin films by reactive magnetron sputtering for the development of a resistive gas sensor
T2 - Verhandlungen der DPG, Berlin 2024
N2 - The use of cerium oxide for hydrogen sensing is limited by the low electrical conductivity of layers deposited from a ceria target. To increase the electrical conductivity, partially reduced cerium oxide layers were obtained from a metallic cerium target by reactive magnetron sputtering. The proportions of the oxidation states Ce3+, present in reduced species, and Ce4+, present in fully oxidized species, were determined by ex-situ XPS. For electrical characterization, films were deposited on planarized tungsten finger electrodes. IV curves were measured over several days to investigate possible influences of oxygen and humidity on electrical conductivity. The morphological stability of the layers under ambient conditions was investigated by microscopical methods. The XPS results show a significant amount of Ce3+ in the layers. The electrical conductivity of as-grown samples is several orders of magnitude higher than that of samples grown from a ceria target. However, the conductivity decreases over time, indicating an oxidation of the layers. The surface morphology of the samples was found to be changing drastically within days, leading to partial delamination.
KW - ceria
KW - metalic cerium target
KW - electrical conductivity
KW - X-ray photoelectron spectroscopy (XPS)
KW - oxidation states
KW - morphology
Y1 - 2024
UR - https://www.dpg-verhandlungen.de/year/2024/conference/berlin/part/ds/session/11/contribution/18
SN - 0420-0195
PB - Deutsche Physikalische Gesellschaft
CY - Bad Honnef
ER -
TY - GEN
A1 - Strobel, Carsten
A1 - Alvarado Chavarin, Carlos
A1 - Knaut, Martin
A1 - Völkel, Sandra
A1 - Albert, Matthias
A1 - Hiess, Andre
A1 - Max, Benjamin
A1 - Wenger, Christian
A1 - Kirchner, Robert
A1 - Mikolajick, Thomas
T1 - High Gain Graphene Based Hot Electron Transistor with Record High Saturated Output Current Density
T2 - Advanced Electronic Materials
N2 - Hot electron transistors (HETs) represent an exciting frontier in semiconductor technology, holding the promise of high-speed and high-frequency electronics. With the exploration of two-dimensional materials such as graphene and new device architectures, HETs are poised to revolutionize the landscape of modern electronics. This study highlights a novel HET structure with a record output current density of 800 A/cm² and a high current gain α, fabricated using a scalable fabrication approach. The HET structure comprises two-dimensional hexagonal boron nitride (hBN) and graphene layers wet transferred to a germanium substrate. The combination of these materials results in exceptional performance, particularly in terms of the highly saturated output current density. The scalable fabrication scheme used to produce the HET opens up opportunities for large-scale manufacturing. This breakthrough in HET technology holds promise for advanced electronic applications, offering high current capabilities in a practical and manufacturable device.
KW - Graphene
KW - Transistor
Y1 - 2024
U6 - https://doi.org/10.1002/aelm.202300624
SN - 2199-160X
VL - 10
IS - 2
ER -
TY - GEN
A1 - Pechmann, Stefan
A1 - Pérez, Eduardo
A1 - Wenger, Christian
A1 - Hagelauer, Amelie
T1 - A current mirror Based read circuit design with multi-level capability for resistive switching deviceb
T2 - 2024 International Conference on Electronics, Information, and Communication (ICEIC)
N2 - This paper presents a read circuit design for resistive memory cells based on current mirrors. The circuit utilizes high-precision current mirrors and reference cells to determine the state of resistive memory using comparators. It offers a high degree in adaptability in terms of both resistance range and number of levels. Special emphasis was put on device protection to prevent accidental programming of the memory during read operations. The realized circuit can resolve eight states with a resolution of up to 1 k Ω, realizing a digitization of the analog memory information. Furthermore, the integration in a complete memory macro is shown. The circuit was realized in a 130 nm-process but can easily be adapted to other processes and resistive memory technologies.
KW - RRAM
KW - memristive device
Y1 - 2024
SN - 979-8-3503-7188-8
U6 - https://doi.org/10.1109/ICEIC61013.2024.10457188
SN - 2767-7699
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
TY - GEN
A1 - Nikiruy, Kristina
A1 - Pérez, Eduardo
A1 - Baroni, Andrea
A1 - Dorai Swamy Reddy, Keerthi
A1 - Pechmann, Stefan
A1 - Wenger, Christian
A1 - Ziegler, Martin
T1 - Blooming and pruning: learning from mistakes with memristive synapses
T2 - Scientific Reports
N2 - AbstractBlooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. This approach provides hardware, local, and energy-efficient learning. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks.
KW - RRAM
KW - Neural network
Y1 - 2024
U6 - https://doi.org/10.1038/s41598-024-57660-4
SN - 2045-2322
VL - 14
IS - 1
ER -
TY - CHAP
A1 - Wen, Jianan
A1 - Vargas, Fabian Luis
A1 - Zhu, Fukun
A1 - Reiser, Daniel
A1 - Baroni, Andrea
A1 - Fritscher, Markus
A1 - Pérez, Eduardo
A1 - Reichenbach, Marc
A1 - Wenger, Christian
A1 - Krstic, Milos
T1 - Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment
T2 - 2024 IEEE 25th Latin American Test Symposium (LATS)
N2 - Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation.
KW - RRAM
Y1 - 2024
U6 - https://doi.org/10.1109/LATS62223.2024.10534601
PB - IEEE
ER -
TY - GEN
A1 - Dorai Swamy Reddy, Keerthi
A1 - Pérez, Eduardo
A1 - Baroni, Andrea
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Marschmeyer, Steffen
A1 - Fraschke, Mirko
A1 - Lisker, Marco
A1 - Wenger, Christian
A1 - Mai, Andreas
T1 - Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance
T2 - The European Physical Journal B
N2 - Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.
KW - RRAM
Y1 - 2024
U6 - https://doi.org/10.1140/epjb/s10051-024-00821-1
SN - 1434-6028
VL - 97
PB - Springer Science and Business Media LLC
ER -
TY - GEN
A1 - Jia, Ruolan
A1 - Pechmann, Stefan
A1 - Markus, Fritscher
A1 - Wenger, Christian
A1 - Zhang, Lei
A1 - Hagelauer, Amelie
T1 - Soft-Error Analysis of RRAM 1T1R Compute-In-Memory Core for Artificial Neural Networks
T2 - 2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)
N2 - This work analyses SEU-induced soft-errors in analog compute-in-memory cores using resistive random-access memory (RRAM) for artificial neural networks, where their bitcells utilize one-transistor-one-RRAM (1T1R) structure. This is modeled by combining the Stanford-PKU RRAM Model and the model of the radiation-induced photocurrent in access transistors. As results, this work derives the maximal RRAM crossbar size without occurring any logic flip and indicates the requirements for RRAM technology to achieve a SEU-resilient 1T1R compute-in memory cores.
KW - RRAM
Y1 - 2024
U6 - https://doi.org/10.1109/DCIS62603.2024.10769203
SP - 1
EP - 5
PB - IEEE
ER -
TY - GEN
A1 - Perez-Bosch Quesada, Emilio
A1 - Mistroni, Alberto
A1 - Jia, Ruolan
A1 - Dorai Swamy Reddy, Keerthi
A1 - Reichmann, Felix
A1 - Castan, Helena
A1 - Dueñas, Salvador
A1 - Wenger, Christian
A1 - Perez, Eduardo
T1 - Forming and resistive switching of HfO₂-based RRAM devices at cryogenic temperature
T2 - IEEE Electron Device Letters
N2 - Reliable data storage technologies able to operate at cryogenic temperatures are critical to implement scalable quantum computers and develop deep-space exploration systems, among other applications. Their scarce availability is pushing towards the development of emerging memories that can perform such storage in a non-volatile fashion. Resistive Random-Access Memories (RRAM) have demonstrated their switching capabilities down to 4K. However, their operability at lower temperatures still remain as a challenge. In this work, we demonstrate for the first time the forming and resistive switching capabilities of CMOS-compatible RRAM devices at 1.4K. The HfO2-based devices are deployed following an array of 1-transistor-1-resistor (1T1R) cells. Their switching performance at 1.4K was also tested in the multilevel-cell (MLC) approach, storing up to 4 resistance levels per cell.
KW - RRAM
Y1 - 2024
U6 - https://doi.org/10.1109/LED.2024.3485873
SN - 0741-3106
VL - 45
IS - 12
SP - 2391
EP - 2394
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
TY - GEN
A1 - Weißhaupt, David
A1 - Sürgers, Christoph
A1 - Bloos, Dominik
A1 - Funk, Hannes Simon
A1 - Oehme, Michael
A1 - Fischer, Gerda
A1 - Schubert, Markus Andreas
A1 - Wenger, Christian
A1 - van Slageren, Joris
A1 - Fischer, Inga Anita
A1 - Schulze, Jörg
T1 - Lateral Mn5Ge3 spin-valve in contact with a high-mobility Ge two-dimensional hole gas
T2 - Semiconductor Science and Technology
N2 - Abstract
Ge two-dimensional hole gases (2DHG) in strained modulation-doped quantum-wells represent a promising material platform for future spintronic applications due to their excellent spin transport properties and the theoretical possibility of efficient spin manipulation. Due to the continuous development of epitaxial growth recipes extreme high hole mobilities and low effective masses can be achieved, promising an efficient spin transport. Furthermore, the Ge 2DHG can be integrated in the well-established industrial complementary metal-oxide-semiconductor (CMOS) devices technology. However, efficient electrical spin injection into a Ge 2DHG—an essential prerequisite for the realization of spintronic devices—has not yet been demonstrated. In this work, we report the fabrication and low-temperature magnetoresistance (MR) measurements of a laterally structured Mn5Ge3/Ge 2DHG/ Mn5Ge3 device. The ferromagnetic Mn5Ge3 contacts are grown directly into the Ge quantum well by means of an interdiffusion process with a spacing of approximately 130 nm, forming a direct electrical contact between the ferromagnetic metal and the Ge 2DHG. Here, we report for the first time a clear MR signal for temperatures below 13 K possibly arising from successful spin injection into the high mobility Ge 2DHG. The results represent a step forward toward the realization of CMOS compatible spintronic devices based on a 2DHG.
KW - two-dimensional hole gas
Y1 - 2024
U6 - https://doi.org/10.1088/1361-6641/ad8d06
SN - 0268-1242
VL - 39
IS - 12
SP - 1
EP - 10
PB - IOP Publishing
ER -
TY - GEN
A1 - Capista, Daniele
A1 - Lukose, Rasuole
A1 - Majnoon, Farnaz
A1 - Lisker, Marco
A1 - Wenger, Christian
A1 - Lukosius, Mindaugas
T1 - Optimization of the metal deposition process for the accurate estimation of Low Metal-Graphene Contact-Resistance
T2 - 47th MIPRO ICT and Electronics Convention (MIPRO), 20-24 May 2024, Opatija, Croatia
Y1 - 2024
SN - 979-8-3503-8250-1
SN - 979-8-3503-8249-5
U6 - https://doi.org/10.1109/MIPRO60963.2024.10569895
SN - 2623-8764
ER -