TY - GEN A1 - Soltani Zarrin, Pouya A1 - Zahari, Finn A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Perez, Eduardo A1 - Kohlstedt, Hermann A1 - Wenger, Christian T1 - Neuromorphic on‑chip recognition of saliva samples of COPD and healthy controls using memristive devices T2 - Scientific Reports N2 - Chronic Obstructive Pulmonary Disease (COPD) is a life-threatening lung disease, affecting millions of people worldwide. Implementation of Machine Learning (ML) techniques is crucial for the effective management of COPD in home-care environments. However, shortcomings of cloud-based ML tools in terms of data safety and energy efficiency limit their integration with low-power medical devices. To address this, energy efficient neuromorphic platforms can be used for the hardware-based implementation of ML methods. Therefore, a memristive neuromorphic platform is presented in this paper for the on-chip recognition of saliva samples of COPD patients and healthy controls. The results of its performance evaluations showed that the digital neuromorphic chip is capable of recognizing unseen COPD samples with accuracy and sensitivity values of 89% and 86%, respectively. Integration of this technology into personalized healthcare devices will enable the better management of chronic diseases such as COPD. KW - RRAM KW - memristive device KW - neural network Y1 - 2020 U6 - https://doi.org/10.1038/s41598-020-76823-7 SN - 2045-2322 VL - 10 ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Lukose, Rasuolė A1 - Lisker, Marco A1 - Luongo, G. A1 - Elviretti, M. A1 - Mai, Andreas A1 - Wenger, Christian T1 - Graphene Research in 200 mm CMOS Pilot Line T2 - 45th Jubilee International Convention on Information, Communication and Electronic Technology (MIPRO), 2022 N2 - Due to the unique electronic structures, graphene and other 2D Materials are considered as materials which can enable and extend the functionalities and performance in a large variety of applications, among them in microelectronics. At this point, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance.Towards these goals, this paper focuses on the full spectra of graphene research aspects in 200mm pilot line. We investigated different process module developments such as CMOS compatible growth of high quality graphene on germanium and its growth mechanisms, transfer related challenges on target substrates, patterning, passivation and various concepts of contacting of graphene on a full 200 mm wafers. Finally, we fabricated proof-of-concept test structures e.g. TLM, Hall bars and capacitor structures to prove the feasibility of graphene processing in the pilot line of IHP. KW - Graphene KW - CMOS Y1 - 2022 SN - 978-953-233-103-5 SN - 978-953-233-102-8 SN - 978-1-6654-8434-3 U6 - https://doi.org/10.23919/MIPRO55190.2022.9803362 SN - 2623-8764 SN - 1847-3938 SP - 113 EP - 117 ER - TY - GEN A1 - Baroni, Andrea A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Perez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - Tackling the Low Conductance State Drift through Incremental Reset and Verify in RRAM Arrays T2 - 2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021 N2 - Resistive switching memory (RRAM) is a promising technology for highly efficient computing scenarios. RRAM arrays enabled the acceleration of neural networks for artificial intelligence and the creation of In-Memory Computing circuits. However, the arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation in those applications. Among those, one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are fundamental for an accurate Multi-level conductance operation. In this work, we tackle the issue by developing an Incremental Reset and Verify technique showing enhanced variability and reliability features compared with a traditional refresh-based approach. KW - RRAM KW - resistive switching KW - neural network Y1 - 2021 SN - 978-1-6654-1794-5 SN - 978-1-6654-1795-2 U6 - https://doi.org/10.1109/IIRW53245.2021.9635613 SN - 2374-8036 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Milo, Valerio A1 - Anzalone, Francesco A1 - Zambelli, Cristian A1 - Perez, Eduardo A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Ossorio, Óscar G. A1 - Olivo, Piero A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - Optimized programming algorithms for multilevel RRAM in hardware neural networks T2 - IEEE International Reliability Physics Symposium (IRPS), 2021 N2 - A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO 2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5% (vs. software 93.27%) in MNIST recognition. KW - RRAM KW - Multilevel switching KW - neural network KW - memristive switching Y1 - 2021 SN - 978-1-7281-6894-4 U6 - https://doi.org/10.1109/IRPS46558.2021.9405119 SN - 1938-1891 ER - TY - GEN A1 - Dirkmann, Sven A1 - Kaiser, Jan A1 - Wenger, Christian A1 - Mussenbrock, Thomas T1 - Filament Growth and Resistive Switching in Hafnium Oxide Memristive Devices T2 - Plasma Sources Science and Technology Y1 - 2018 U6 - https://doi.org/10.1021/acsami.7b19836 SN - 1361-6595 SN - 0963-0252 VL - 10 IS - 17 SP - 14857 EP - 14868 ER - TY - GEN A1 - Strobel, Carsten A1 - Alvarado Chavarin, Carlos A1 - Völkel, Sandra A1 - Jahn, Andreas A1 - Hiess, Andre A1 - Knaut, Martin A1 - Albert, Matthias A1 - Wenger, Christian A1 - Steinke, Olaff A1 - Stephan, Ulf A1 - Röhlecke, Sören A1 - Mikolajick, Thomas T1 - Enhanced Electrical Properties of Optimized Vertical Graphene-Base Hot Electron Transistors T2 - ACS Applied Electronic Materials N2 - The arrival of high-mobility two-dimensional materials like graphene leads to the renaissance of former vertical semiconductor–metal–semiconductor (SMS) hot electron transistors. Because of the monolayer thickness of graphene, improved SMS transistors with a semimetallic graphene-base electrode are now feasible for high-frequency applications. In this study we report about a device that consists of amorphous silicon, graphene, and crystalline silicon. For the first time, this device is fabricated by a four-mask lithography process which leads to significant improvements in the device performance. A strongly increased common-emitter current gain of 2% could be achieved while the on–off ratio improved to 1.6 × 105, which is already higher than predicted theoretically. This could be mainly attributed to better interface characteristics and decreased lateral dimensions of the devices. A cutoff frequency of approximately 26 MHz could be forecasted based on the DC measurements of the device. KW - Graphene KW - Transistor Y1 - 2023 U6 - https://doi.org/10.1021/acsaelm.2c01725 SN - 2637-6113 VL - 5 IS - 3 SP - 1670 EP - 1675 ER - TY - GEN A1 - Strobel, Carsten A1 - Alvarado Chavarin, Carlos A1 - Richter, Karola A1 - Knaut, Martin A1 - Reif, Johanna A1 - Völkel, Sandra A1 - Jahn, Andreas A1 - Albert, Matthias A1 - Wenger, Christian A1 - Kirchner, Robert A1 - Bartha, Johann Wolfgang A1 - Mikolajick, Thomas T1 - Novel Graphene Adjustable-Barrier Transistor with Ultra-High Current Gain T2 - ACS Applied Materials & Interfaces N2 - A graphene-based three terminal barristor device was proposed to overcome the low on/off ratios and insufficient current saturation of conventional graphene field effect transistors. In this study, we fabricated and analyzed a novel graphene-based transistor, which resembles the structure of the barristor but uses a different operating condition. This new device, termed graphene adjustable-barriers transistor (GABT), utilizes a semiconductor-based gate rather than a metal−insulator gate structure to modulate the device currents. The key feature of the device is the two graphene-semiconductor Schottky barriers with different heights that are controlled simultaneously by the gate voltage. Due to the asymmetry of the barriers, the drain current exceeds the gate current by several orders of magnitude. Thus, the GABT can be considered an amplifier with an alterable current gain. In this work, a silicon−graphene−germanium GABT with an ultra-high current gain (ID/IG up to 8 × 106) was fabricated, and the device functionality was demonstrated. Additionally, a capacitance model is applied to predict the theoretical device performance resulting in an on−off ratio above 106, a swing of 87 mV/dec, and a drivecurrent of about 1 × 106 A/cm2. KW - Graphene KW - Transistor Y1 - 2022 U6 - https://doi.org/10.1021/acsami.2c10634 SN - 1944-8244 SN - 1944-8252 VL - 14 IS - 34 SP - 39249 EP - 39254 ER - TY - GEN A1 - Mahmoodinezhad, Ali A1 - Morales, Carlos A1 - Naumann, Franziska A1 - Plate, Paul A1 - Meyer, Robert A1 - Janowitz, Christoph A1 - Henkel, Karsten A1 - Kot, Małgorzata A1 - Zöllner, Marvin Hartwig A1 - Wenger, Christian A1 - Flege, Jan Ingo T1 - Low-temperature atomic layer deposition of indium oxide thin films using trimethylindium and oxygen plasma T2 - Journal of Vacuum Science and Technology A N2 - Indium oxide (InxOy) thin films were deposited by plasma-enhanced atomic layer deposition (PEALD) using trimethylindium and oxygen plasma in a low-temperature range of 80–200 °C. The optical properties, chemical composition, crystallographic structure, and electrical characteristics of these layers were investigated by spectroscopic ellipsometry (SE), x-ray photoelectron spectroscopy (XPS), x-ray diffraction (XRD), as well as current-voltage and capacitance-voltage measurements. The SE results yielded a nearly constant growth rate of 0.56 Å per cycle and a thickness inhomogeneity of ≤1.2% across 4-in. substrates in the temperature range of 100–150 °C. The refractive index (at 632.8 nm) was found to be 2.07 for the films deposited at 150 °C. The PEALD-InxOy layers exhibit a direct (3.3 ± 0.2 eV) and an indirect (2.8 ± 0.1 eV) bandgap with an uptrend for both with increasing substrate temperature. Based on XPS characterization, all InxOy samples are free of carbon impurities and show a temperature-dependent off-stoichiometry indicating oxygen vacancies. XRD diffraction patterns demonstrate an onset of crystallization at 150 °C. Consistent with the optical, XPS, and XRD data, the films deposited at ≥150 °C possess higher electrical conductivity. Our findings prove that a low-temperature PEALD process of InxOy is feasible and promising for a high-quality thin-film deposition without chemical impurities on thermally fragile substrates. KW - Indium oxide KW - Plasma-enhanced atomic layer deposition KW - X-ray photoelectron spectroscopy KW - Ellipsometry KW - X-ray diffraction KW - Electrical properties Y1 - 2021 U6 - https://doi.org/10.1116/6.0001375 SN - 0734-2101 SN - 1520-8559 VL - 39 IS - 6 ER - TY - GEN A1 - Janowitz, Christoph A1 - Mahmoodinezhad, Ali A1 - Kot, Małgorzata A1 - Morales, Carlos A1 - Naumann, Franziska A1 - Plate, Paul A1 - Zöllner, Marvin Hartwig A1 - Bärwolf, Florian A1 - Stolarek, David A1 - Wenger, Christian A1 - Henkel, Karsten A1 - Flege, Jan Ingo T1 - Toward controlling the Al2O3/ZnO interface properties by in situ ALD preparation T2 - Dalton Transactions N2 - An Al2O3/ZnO heterojunction was grown on a Si single crystal substrate by subsequent thermal and plasma-assisted atomic layer deposition (ALD) in situ. The band offsets of the heterointerface were then studied by consecutive removal of the layers by argon sputtering, followed by in situ X-ray photoelectron spectroscopy. The valence band maximum and conduction band minimum of Al2O3 are found to be 1.1 eV below and 2.3 eV above those of ZnO, resulting in a type-I staggered heterojunction. An apparent reduction of ZnO to elemental Zn in the interface region was detected in the Zn 2p core level and Zn L3MM Auger spectra. This suggests an interface formation different from previous models. The reduction of ZnO to Zn in the interface region accompanied by the creation of oxygen vacancies in ZnO results in an upward band bending at the interface. Therefore, this study suggests that interfacial properties such as the band bending as well as the valence and conduction band offsets should be in situ controllable to a certain extent by careful selection of the process parameters. KW - ALD heterojunction KW - band alignement KW - ZnO KW - Al2O3 KW - interface properties Y1 - 2022 U6 - https://doi.org/10.1039/D1DT04008A SN - 1477-9234 SN - 1477-9226 VL - 51 SP - 9291 EP - 9301 ER - TY - GEN A1 - Fritscher, Markus A1 - Knödtel, Johannes A1 - Mallah, Maen A1 - Pechmann, Stefan A1 - Perez-Bosch Quesada, Emilio A1 - Rizzi, Tommaso A1 - Wenger, Christian A1 - Reichenbach, Marc T1 - Mitigating the Effects of RRAM Process Variation on the Accuracy of Artifical Neural Networks T2 - Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science N2 - Weight storage is a key challenge in the efficient implementation of artificial neural networks. Novel memory technologies such as RRAM are able to greatly improve density and introduce non-volatility and multibit capabilities to this component of ANN accelerators. The usage of RRAM in this domain comes with downsides, mainly caused by cycle-to-cycle and device-to-device variability leading to erroneous readouts, greatly affecting digital systems. ANNs have the ability to compensate for this by their inherent redundancy and usually exhibit a gradual deterioration in the accuracy of the task at hand. This means, that slight error rates can be acceptable for weight storage in an ANN accelerator. In this work we link device-to-device variability to the accuracy of an ANN for such an accelerator. From this study, we can estimate how strongly a certain net is affected by a certain device parameter variability. This methodology is then used to present three mitigation strategies and to evaluate how they affect the reaction of the network to variability: a) Dropout Layers b) Fault-Aware Training c) Redundancy. These mitigations are then evaluated by their ability to improve accuracy and to lower hardware overhead by providing data for a real-word example. We improved this network’s resilience in such a way that it could tolerate double the variation in one of the device parameters (standard deviation of the oxide thickness can be 0.4 nm instead of 0.2 nm while maintaining sufficient accuracy.) KW - RRAM KW - memristive device KW - neural network Y1 - 2022 SN - 978-3-031-04579-0 SN - 978-3-031-04580-6 U6 - https://doi.org/10.1007/978-3-031-04580-6_27 SN - 0302-9743 SN - 1611-3349 SP - 401 EP - 417 PB - Springer ER -