TY - GEN A1 - Perez-Avila, Antonio Javier A1 - Gonzalez-Cordero, Gerardo A1 - Perez, Eduardo A1 - Perez-Bosch Quesada, Emilio A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Wenger, Christian A1 - Roldan, Juan Bautista A1 - Jimenez-Molinos, Francisco T1 - Behavioral modeling of multilevel HfO2-based memristors for neuromorphic circuit simulation T2 - XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain N2 - An artificial neural network based on resistive switching memristors is implemented and simulated in LTspice. The influence of memristor variability and the reduction of the continuous range of synaptic weights into a discrete set of conductance levels is analyzed. To do so, a behavioral model is proposed for multilevel resistive switching memristors based on Al-doped HfO2 dielectrics, and it is implemented in a spice based circuit simulator. The model provides an accurate description of the conductance in the different conductive states in addition to describe the device-to-device variability KW - RRAM KW - Multilevel switching KW - behavorial model Y1 - 2020 U6 - https://doi.org/10.1109/DCIS51330.2020.9268652 ER - TY - GEN A1 - Morales, Carlos A1 - Mahmoodinezhad, Ali A1 - Schubert, Andreas Markus A1 - Wenger, Christian A1 - Henkel, Karsten A1 - Flege, Jan Ingo T1 - Functional ultra-thin oxide films deposited by atomic layer deposition on structured substrates T2 - Verhandlungen der DPG - SurfaceScience21 N2 - In the last decades, atomic layer deposition (ALD) has gained prominence in the materials and surface science communities owing to its high potential for integration as a scalable process in microelectronics. ALD's largest strengths are its well-controlled layer-by-layer deposition and growth conformity on 3D structures. Yet, the ALD technique is also well known to lead to amorphous and defective, non-stoichiometric thin films, resulting in modified materials properties that may even preferentially be used in certain applications. To study these issues, we have developed an in-situ ALD reactor attached to an X-ray photoelectron spectroscopy (XPS) system, capable of switching between both pump and flow-type operation. This novel tool allows to cover the entire range of compounds and recipes used in ALD, thus clarifying the role of such defects at different deposition stages, growth conditions and film/substrate interfaces. To exemplify these sorts of studies, we show the deposition of Al2O3 5-10 nm films on nanostructured Si, and their use as substrates for functional CeOx ALD deposits. KW - Atomic layer deposition KW - sensors KW - structured substrates KW - in-situ X-ray photoelectron spectroscopy Y1 - 2021 UR - https://www.dpg-verhandlungen.de/year/2021/conference/surfacescience/part/o/session/74/contribution/5 VL - 2021 PB - Deutsche Physikalische Gesellschaft e.V. CY - Bad Honnef ER - TY - GEN A1 - Perez, Eduardo A1 - Pérez-Ávila, Antonio Javier A1 - Romero-Zaliz, Rocío A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Pérez-Bosch Quesada, Emilio A1 - Roldan, Juan Bautista A1 - Jiménez-Molinos, Francisco A1 - Wenger, Christian T1 - Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing T2 - Electronics (MDPI) N2 - Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8×8 vector-matrixmultiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters. KW - RRAM KW - Multilevel switching KW - In-memory computing Y1 - 2021 U6 - https://doi.org/10.3390/electronics10091084 SN - 2079-9292 VL - 10 IS - 9 ER - TY - GEN A1 - Perez, Eduardo A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Perez-Bosch Quesada, Emilio A1 - Wenger, Christian T1 - Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays T2 - IEEE Transactions on Electron Devices N2 - Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm to employ should be based on the specific application targeted for the RRAM array. KW - RRAM KW - Multilevel switching KW - HfO2 Y1 - 2021 U6 - https://doi.org/10.1109/TED.2021.3072868 SN - 0018-9383 SN - 1557-9646 VL - 68 IS - 6 SP - 2693 EP - 2698 ER - TY - GEN A1 - Romero-Zaliz, Rocío A1 - Perez, Eduardo A1 - Jimenez-Molinos, Francisco A1 - Wenger, Christian A1 - Roldan, Juan Bautista T1 - Influence of variability on the performance of HfO2 memristor-based convolutional neural networks T2 - Solid State Electronics N2 - A study of convolutional neural networks (CNNs) was performed to analyze the influence of quantization and variability in the network synaptic weights. Different CNNs were considered accounting for the number of convolutional layers, size of the filters in the convolutional layer, number of neurons in the final network layers and different sets of quantization levels. The conductance levels of fabricated 1T1R structures based on HfO2 memristors were considered as reference for four or eight level quantization processes at the inference stage of the CNNs, which were previous trained with the MNIST dataset. We also included the variability of the experimental conductance levels that was found to be Gaussian distributed and was correspondingly modeled for the synaptic weight implementation. KW - RRAM KW - neural network KW - HfO2 KW - memristive switching Y1 - 2021 U6 - https://doi.org/10.1016/j.sse.2021.108064 SN - 0038-1101 VL - 185 ER - TY - GEN A1 - Yun, Min Ju A1 - Lee, Doowon A1 - Kim, Sungho A1 - Wenger, Christian A1 - Kim, Hee-Dong T1 - A nonlinear resistive switching behaviors of Ni/HfO2/TiN memory structures for self-rectifying resistive switching memory T2 - Materials Characterization N2 - This work reports forming free/self-rectifying resistive switching characteristics and dependency of the top electrode (TE) of a crystalline HfO2-based resistive switching memory device. In the memory cells, nonlinear bipolar resistive switching characteristics, i.e., an asymmetric current-voltage curve like the Schottky diode, was observed. In addition, the device exhibits resistive switching behaviors without forming process, which makes it possible to switch the resistance state under ultra-low current levels of <10 nA. In addition, compared to the resistive switching of the proposed resistive switching memory devices with different TEs, the VSET was decreased when using TE with lower work function, and the height read margin was obtained in the sample with the Ni TE, covering over 56 × 56 arrays. Consequently, these results indicate that the interface control resistive switching properties in memory structures having the Schottky junction warrant the realization of selector-free resistive switching memory cells in a high-density crossbar array. KW - RRAM KW - resistive switching KW - HfO2 Y1 - 2021 U6 - https://doi.org/10.1016/j.matchar.2021.111578 SN - 1044-5803 VL - 182 ER - TY - GEN A1 - Perez-Bosch Quesada, Emilio A1 - Perez, Eduardo A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Wenger, Christian T1 - Memristive-based in-memory computing: from device to large-scale CMOS integration T2 - Neuromorphic Computing and Engineering N2 - With the rapid emergence of in-memory computing systems based on memristive technology, the integration of such memory devices in large-scale architectures is one of the main aspects to tackle. In this work we present a study of HfO2-based memristive devices for their integration in large-scale CMOS systems, namely 200 mm wafers. The DC characteristics of single metal–insulator–metal devices are analyzed taking under consideration device-to-device variabilities and switching properties. Furthermore, the distribution of the leakage current levels in the pristine state of the samples are analyzed and correlated to the amount of formingless memristors found among the measured devices. Finally, the obtained results are fitted into a physic-based compact model that enables their integration into larger-scale simulation environments. KW - RRAM KW - memristive device KW - HfO2 Y1 - 2021 U6 - https://doi.org/10.1088/2634-4386/ac2cd4 SN - 2634-4386 VL - 1 IS - 2 ER - TY - GEN A1 - Romero-Zaliz, Rocio A1 - Cantudo, Antonio A1 - Perez, Eduardo A1 - Jimenez-Molinos, Francisco A1 - Wenger, Christian A1 - Roldan, Juan Bautista T1 - An Analysis on the Architecture and the Size of Quantized Hardware Neural Networks Based on Memristors T2 - Electronics (MDPI) N2 - We have performed different simulation experiments in relation to hardware neural networks (NN) to analyze the role of the number of synapses for different NN architectures in the network accuracy, considering different datasets. A technology that stands upon 4-kbit 1T1R ReRAM arrays, where resistive switching devices based on HfO2 dielectrics are employed, is taken as a reference. In our study, fully dense (FdNN) and convolutional neural networks (CNN) were considered, where the NN size in terms of the number of synapses and of hidden layer neurons were varied. CNNs work better when the number of synapses to be used is limited. If quantized synaptic weights are included, we observed thatNNaccuracy decreases significantly as the number of synapses is reduced; in this respect, a trade-off between the number of synapses and the NN accuracy has to be achieved. Consequently, the CNN architecture must be carefully designed; in particular, it was noticed that different datasets need specific architectures according to their complexity to achieve good results. It was shown that due to the number of variables that can be changed in the optimization of a NN hardware implementation, a specific solution has to be worked in each case in terms of synaptic weight levels, NN architecture, etc. KW - RRAM KW - memristive device KW - neural network Y1 - 2021 U6 - https://doi.org/10.3390/electronics10243141 SN - 2079-9292 VL - 10 IS - 24 ER - TY - GEN A1 - Bischoff, Carl A1 - Leise, Jakob A1 - Perez-Bosch Quesada, Emilio A1 - Perez, Eduardo A1 - Wenger, Christian A1 - Kloes, Alexander T1 - Implementation of device-to-device and cycle-to-cycle variability of memristive devices in circuit simulations T2 - Solid-State Electronics N2 - We present a statistical procedure for the extraction of parameters of a compact model for memristive devices. Thereby, in a circuit simulation the typical fluctuations of the current–voltage (I-V) characteristics from device-to-device (D2D) and from cycle-to-cycle (C2C) can be emulated. The approach is based on the Stanford model whose parameters play a key role to integrating D2D and C2C dispersion. The influence of such variabilities over the model’s parameters is investigated by using a fitting algorithm fed with experimental data. After this, the statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of RRAM cells or memristor-based artificial neural networks. KW - RRAM KW - circuit simulation KW - HfO2 Y1 - 2022 U6 - https://doi.org/10.1016/j.sse.2022.108321 SN - 0038-1101 VL - 194 ER - TY - GEN A1 - Mannocci, Piergiulio A1 - Baroni, Andrea A1 - Melacarne, Enrico A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Perez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - In-Memory Principal Component Analysis by Crosspoint Array of Rresistive Switching Memory T2 - IEEE Nanotechnology Magazine N2 - In Memory Computing (IMC) is one of the most promising candidates for data-intensive computing accelerators of machine learning (ML). A key ML algorithm for dimensionality reduction and classification is principal component analysis (PCA), which heavily relies on matrixvector multiplications (MVM) for which classic von Neumann architectures are not optimized. Here, we provide the experimental demonstration of a new IMCbased PCA algorithm based on power iteration and deflation executed in a 4-kbit array of resistive switching random-access memory (RRAM). The classification accuracy of the Wisconsin Breast Cancer data set reaches 95.43%, close to floatingpoint implementation. Our simulations indicate a 250× improvement in energy efficiency compared to commercial GPUs, thus supporting IMC for energy-efficient ML in modern data-intensive computing. KW - RRAM KW - Multilevel switching KW - neural network Y1 - 2022 U6 - https://doi.org/10.1109/MNANO.2022.3141515 SN - 1932-4510 VL - 16 IS - 2 SP - 4 EP - 13 ER - TY - GEN A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Perez, Eduardo A1 - Lisker, Marco A1 - Schubert, Markus Andreas A1 - Perez-Bosch Quesada, Emilio A1 - Wenger, Christian A1 - Mai, Andreas T1 - Modulating the Filamentary-Based Resistive Switching Properties of HfO2 Memristive Devices by Adding Al2O3 Layers T2 - Electronics : open access journal N2 - The resistive switching properties of HfO2 based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al2O3 into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I–V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit. KW - RRAM KW - HfO2 KW - filamentary switching Y1 - 2022 U6 - https://doi.org/10.3390/electronics11101540 SN - 2079-9292 VL - 11 IS - 10 ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Perez, Eduardo A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages T2 - 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) N2 - RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states. KW - RRAM KW - Multilevel switching KW - AI accelarator Y1 - 2022 SN - 978-1-6654-5938-9 SN - 978-1-6654-5937-2 U6 - https://doi.org/10.1109/DFT56152.2022.9962345 SN - 2765-933X SP - 1 EP - 6 ER - TY - GEN A1 - Akhtar, Fatima A1 - Dabrowski, Jaroslaw A1 - Lukose, Rasuole A1 - Wenger, Christian A1 - Lukosius, Mindaugas T1 - Chemical Vapor Deposition Growth of Graphene on 200 mm Ge (110)/Si Wafers and Ab Initio Analysis of Differences in Growth Mechanisms on Ge (110) and Ge (001) T2 - ACS Applied Materials & Interfaces N2 - For the fabrication of modern graphene devices, uniform growth of high-quality monolayer graphene on wafer scale is important. This work reports on the growth of large-scale graphene on semiconducting 8 inch Ge(110)/Si wafers by chemical vapor deposition and a DFT analysis of the growth process. Good graphene quality is indicated by the small FWHM (32 cm–1) of the Raman 2D band, low intensity ratio of the Raman D and G bands (0.06), and homogeneous SEM images and is confirmed by Hall measurements: high mobility (2700 cm2/Vs) and low sheet resistance (800 Ω/sq). In contrast to Ge(001), Ge(110) does not undergo faceting during the growth. We argue that Ge(001) roughens as a result of vacancy accumulation at pinned steps, easy motion of bonded graphene edges across (107) facets, and low energy cost to expand Ge area by surface vicinals, but on Ge(110), these mechanisms do not work due to different surface geometries and complex reconstruction. KW - Graphene KW - Chemical Vapor Deposition Y1 - 2023 U6 - https://doi.org/10.1021/acsami.3c05860 SN - 1944-8244 VL - 15 IS - 30 SP - 36966 EP - 36974 ER - TY - GEN A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Glukhov, Artem A1 - Bertozzi, Davide A1 - Wenger, Christian A1 - Ielmini, Daniele A1 - Zambelli, Cristian T1 - Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAs T2 - IEEE Transactions on Device and Materials Reliability N2 - Resistive Random Access Memory (RRAM) technology holds promises to improve the Field Programmable Gate Array (FPGA) performance, reduce the area footprint, and dramatically lower run-time energy requirements compared to the state-of-the-art CMOS-based products. However, the integration of RRAM in FPGAs is hindered by the high programming power consumption and by non-ideal behaviors of the device due to its stochastic nature that may overshadow the benefits in normal operation mode. To cope with these challenges, optimized programming strategies have to be investigated. In this work, we explore the impact that different procedures to set the device have on the run-time performance. Process, voltage, and temperature (PVT) variations as well as time-dependent drift effect of the RRAM device are considered in the assessment of 4T1R MUX designs characteristics. The comparison with tradition CMOS implementations reveals how the choice of the target resistive state and the programming algorithm are key design aspects to reduce the run-time delay and energy metrics, while at the same time improving the robustness against the different sources of variations. KW - RRAM KW - FPGA Y1 - 2023 U6 - https://doi.org/10.1109/TDMR.2023.3259015 SN - 1530-4388 VL - 23 IS - 3 SP - 328 EP - 336 ER - TY - GEN A1 - Perez, Eduardo A1 - Maldonado, David A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Perez-Bosch Quesada, Emilio A1 - Cantudo, Antonio A1 - Jimenez-Molinos, Francisco A1 - Wenger, Christian A1 - Roldan, Juan Bautista T1 - A comparison of resistive switching parameters for memristive devices with HfO2 monolayers and Al2O3/HfO2 bilayers at the wafer scale T2 - 14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023 N2 - Memristive devices integrated in 200 mm wafers manufactured in 130 nm CMOS technology with two different dielectrics, namely, a HfO2 monolayer and an Al2O3/HfO2 bilayer, have been measured. The cycle-to-cycle (C2C) and device-todevice (D2D) variability have been analyzed at the wafer scale using different numerical methods to extract the set (Vset) and reset (Vreset) voltages. Some interesting differences between both technologies were found in terms of switching characteristics KW - RRAM Y1 - 2023 SN - 979-8-3503-0240-0 U6 - https://doi.org/10.1109/CDE58627.2023.10339417 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Morales, Carlos A1 - Mahmoodinezhad, Ali A1 - Tschammer, Rudi A1 - Kosto, Yuliia A1 - Alvarado Chavarin, Carlos A1 - Schubert, Markus Andreas A1 - Wenger, Christian A1 - Henkel, Karsten A1 - Flege, Jan Ingo T1 - Combination of Multiple Operando and In-Situ Characterization Techniques in a Single Cluster System for Atomic Layer Deposition: Unraveling the Early Stages of Growth of Ultrathin Al2O3 Films on Metallic Ti Substrates T2 - Inorganics N2 - This work presents a new ultra-high vacuum cluster tool to perform systematic studies of the early growth stages of atomic layer deposited (ALD) ultrathin films following a surface science approach. By combining operando (spectroscopic ellipsometry and quadrupole mass spectrometry) and in situ (X-ray photoelectron spectroscopy) characterization techniques, the cluster allows us to follow the evolution of substrate, film, and reaction intermediates as a function of the total number of ALD cycles, as well as perform a constant diagnosis and evaluation of the ALD process, detecting possible malfunctions that could affect the growth, reproducibility, and conclusions derived from data analysis. The homemade ALD reactor allows the use of multiple precursors and oxidants and its operation under pump and flow-type modes. To illustrate our experimental approach, we revisit the well-known thermal ALD growth of Al2O3 using trimethylaluminum and water. We deeply discuss the role of the metallic Ti thin film substrate at room temperature and 200 °C, highlighting the differences between the heterodeposition (<10 cycles) and the homodeposition (>10 cycles) growth regimes at both conditions. This surface science approach will benefit our understanding of the ALD process, paving the way toward more efficient and controllable manufacturing processes. KW - Atomic layer deposition (ALD) KW - in-situ KW - operando KW - X-ray photoelectron spectroscopy KW - ellipsometry KW - quadrupol mass spectrometry (QMS) Y1 - 2023 U6 - https://doi.org/10.3390/inorganics11120477 SN - 2304-6740 VL - 11 IS - 12 ER - TY - GEN A1 - Capista, Daniele A1 - Lukose, Rasuole A1 - Majnoon, Farnaz A1 - Lisker, Marco A1 - Wenger, Christian A1 - Lukosius, Mindaugas T1 - Study on the metal -graphene contact resistance achieved with one -dimensional contact architecture T2 - IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), Paestum, Italy, 22-25 October 2023 N2 - Graphene has always been considered as one of the materials with the greatest potential for the realization of improved microelectronic and photonic devices. But to actually reach its full potential in Si CMOS technology, graphene -based devices need to overcome different challenges. They do not only need to have better performances than standard devices, but they also need to be compatible with the production of standard Si based devices. To address the first challenge the main route requires the optimization of the contact resistance, that highly reduces the devices performance, while the second challenges requires the integration of graphene inside the standard production lines used for microelectronic. In this work we used an 8” wafer pilot -line to realize our devices and we studied the behavior of the contact resistance between metal and graphene obtained by one -dimensional contact architecture between the two materials. The contact resistance has been measured by means of Transmission Line Method (TLM) with several contact patterning. KW - Graphene Y1 - 2023 SN - 979-8-3503-3546-0 U6 - https://doi.org/10.1109/NMDC57951.2023.10343775 SP - 118 EP - 119 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Lukosius, Mindaugas A1 - Lukose, Rasuolė A1 - Lisker, Marco A1 - Dubey, P. K. A1 - Raju, A. I. A1 - Capista, Daniele A1 - Majnoon, Farnaz A1 - Mai, A. A1 - Wenger, Christian T1 - Developments of Graphene devices in 200 mm CMOS pilot line T2 - Proc. Nanotechnology Materials and Devices Conference (NMDC 2023),Paestum, Italy, 22-25 October 2023 N2 - Due to the unique electronic band structure, graphene has opened great potential to extend the functionality of a large variety of devices. Despite the significant progress in the fabrication of various graphene based microelectronic devices, the integration of graphene devices still lack the stability and compatibility with Si-technology processes. Therefore, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance. This study aims to explore various aspects of graphene research on a 200mm pilot line, with a focus on simulations and fabrication of graphene modulator. To be more precise, it includes design and fabrication of the layouts, necessary mask sets, creation of the flows, fabrication, and measurements of the Gr modulators on 200 mm wafers. KW - Graphene Y1 - 2023 SN - 979-8-3503-3546-0 U6 - https://doi.org/10.1109/NMDC57951.2023.10343569 SP - 505 EP - 506 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Maldonado, David A1 - Cantudo, Antonio A1 - Perez, Eduardo A1 - Romero-Zaliz, Rocio A1 - Perez-Bosch Quesada, Emilio A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Jimenez-Molinos, Francisco A1 - Wenger, Christian A1 - Roldan, Juan Bautista T1 - TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance T2 - Frontiers in Neuroscience N2 - We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics. KW - RRAM KW - Neural network Y1 - 2023 U6 - https://doi.org/10.3389/fnins.2023.1271956 SN - 1662-4548 VL - 17 ER - TY - JOUR A1 - Sohal, Rakesh A1 - Lupina, Grzegorz A1 - Lippert, Gunther A1 - Wenger, Christian A1 - Seifarth, Olaf A1 - Schröder, Thomas A1 - Tallarida, Massimo A1 - Schmeißer, Dieter T1 - Interface chemistry of high-k PrxAl2-xO3 (x=2-0) dielectrics on TiN for dynamic random access memory applications KW - high-k KW - dielectric KW - random Y1 - 2008 ER -