TY - GEN
A1 - Kaletta, Udo Christian
A1 - Wipf, Christian
A1 - Fraschke, Mirko
A1 - Wolansky, Dirk
A1 - Schubert, Markus Andreas
A1 - Schroeder, Thomas
A1 - Wenger, Christian
T1 - AlN/SiO2/Si3N4/Si(100) based CMOS compatible surface acoustic wave filter with -12.8 dB minimum insertion loss
T2 - IEEE Transactions on Electron Devices
Y1 - 2015
U6 - https://doi.org/10.1109/TED.2015.2395443
SN - 0018-9383
VL - 62
IS - 3
SP - 764
EP - 768
ER -
TY - GEN
A1 - Bertaud, Thomas
A1 - Walczyk, Damian
A1 - Walczyk, Christian
A1 - Kubotsch, S.
A1 - Wenger, Christian
A1 - Schröder, Thomas
A1 - Vallée, Christophe
A1 - Gonon, P.
A1 - Mannequin, C.
A1 - Jousseaume, V.
A1 - Grampeix, Helen
T1 - Resistive Switching of HfO2-based MIM diodes: Impact of the Top Electrode Materials
T2 - Thin Solid Films
Y1 - 2012
SN - 0040-6090
VL - 520
IS - 14
SP - 4551
EP - 4555
ER -
TY - GEN
A1 - Bertaud, Thomas
A1 - Walczyk, Damian
A1 - Sowinska, Małgorzata
A1 - Wolansky, Dirk
A1 - Tillack, Bernd
A1 - Schoof, Gunther
A1 - Korolevych, R.
A1 - Wenger, Christian
A1 - Thiess, Sebastian
A1 - Schroeder, Thomas
A1 - Walczyk, Christian
T1 - HfO2-based RRAM for Embedded Nonvolatile Memory: From Materials Science to Integrated 1T1R RRAM Arrays
T2 - ECS transactions
Y1 - 2012
SN - 1938-6737
VL - 50
IS - 4
SP - 21
EP - 26
ER -
TY - GEN
A1 - Pérez, Eduardo
A1 - Maldonado, David
A1 - Acal, Christian
A1 - Ruiz-Castro, Juan Eloy
A1 - Aguilera, Ana María
A1 - Jimenez-Molinos, Francisco
A1 - Roldan, Juan Bautista
A1 - Wenger, Christian
T1 - Advanced Temperature Dependent Statistical Analysis of Forming Voltage Distributions for Three Different HfO2-Based RRAM Technologies
T2 - Solid State Electronics
N2 - In this work, voltage distributions of forming operations are analyzed by using an advanced statistical approach based on phase-type distributions (PHD). The experimental data were collected from batches of 128 HfO2-based RRAM devices integrated in 4-kbit arrays. Three di erent switching oxides, namely, polycrystalline HfO2, amorphous HfO2, and Al-doped HfO2, were tested in the temperature range from -40 to 150 oC. The variability of forming voltages has been usually studied by using the Weibull distribution (WD). However, the performance of the PHD analysis demonstrated its ability to better model this crucial operation. The capacity of the PHD to reproduce the experimental data has been validated by means of the Kolmogorov-Smirnov test, while the WD failed in many of the cases studied. In addition, PHD allows to extract information about intermediate probabilistic states that occur in the forming process and the transition probabilities between them; in this manner, we can deepen on the conductive lament formation physics. In particular, the number of intermediate states can be related to the device variability.
KW - RRAM
KW - HfO2
Y1 - 2021
SN - 0038-1101
SN - 1879-2405
VL - 176
ER -
TY - GEN
A1 - Mai, Christian
A1 - Marschmeyer, Steffen
A1 - Peczek, Anna
A1 - Kroh, Aleksandra
A1 - Jose, Josmy
A1 - Reiter, Sebastian
A1 - Fischer, Inga Anita
A1 - Wenger, Christian
A1 - Mai, Andreas
T1 - Integration Aspects of Plasmonic TiN-based Nano-Hole-Arrays on Ge Photodetectorsin a 200mm Wafer CMOS Compatible Silicon Technology
T2 - ECS Transactions
N2 - In this work we present the progress in regard to the integration of a surface plasmon resonance refractive index sensor into a CMOS compatible 200 mm wafer silicon-based technology. Our approach pursues the combination of germanium photodetectors with metallic nanohole arrays. The paper is focused on the technology development to fabricate large area photodetectors based on a modern design concept. In a first iteration we achieved a leakage current density of 82 mA/cm2 at reverse bias of 0.5 V and a maximum optical responsivity of 0.103 A/W measured with TE polarized light at λ = 1310 nm and a reversed bias of 1 V. For the realization of nanohole arrays we used thin Titanium nitride (TiN) layers deposited by a sputtering process. We were able to produce very homogenous TiN layers with a thickness deviation of around 10 % and RMS of 1.413 nm for 150 nm thick TiN layers.
KW - plasmonics
KW - nanohole array
KW - germanium detector
Y1 - 2022
U6 - https://doi.org/10.1149/10904.0035ecst
SN - 1938-5862
VL - 109
IS - 4
SP - 35
EP - 46
ER -
TY - GEN
A1 - Reiter, Sebastian
A1 - Sengül, Akant
A1 - Mai, Christian
A1 - Spirito, Davide
A1 - Wenger, Christian
A1 - Fischer, Inga Anita
T1 - On-chip refractive index sensors based on plasmonic TiN Nanohole Arrays
T2 - 2024 IEEE Silicon Photonics Conference (SiPhotonics)
Y1 - 2024
SN - 979-8-3503-9404-7
SN - 979-8-3503-9405-4
U6 - https://doi.org/10.1109/SiPhotonics60897.2024.10544048
SN - 1949-209X
ER -
TY - GEN
A1 - Jose, Josmy
A1 - Mai, Christian
A1 - Wenger, Christian
A1 - Fischer, Inga Anita
T1 - Integration concept of plasmonic TiN nanohole arrays in a 200 mm BiCMOS Si technology for refractive index sensor applications
T2 - iCCC2024 - iCampµs Cottbus Conference
Y1 - 2024
U6 - https://doi.org/10.5162/iCCC2024/7.2
SP - 96
EP - 99
ER -
TY - GEN
A1 - Mai, Christian
A1 - Peczek, Anna
A1 - Kroh, Aleksandra
A1 - Jose, Josmy
A1 - Reiter, Sebastian
A1 - Wenger, Christian
A1 - Fischer, Inga Anita
T1 - Towards a CMOS compatible refractive index sensor: cointegration of TiN nanohole arrays and Ge photodetectors in a 200 mm wafer silicon technology
T2 - Optics Express
N2 - In this work, we present the monolithic integration of a TiN nanohole array and a Ge photodetector towards a CMOS compatible fabrication of a refractive index sensor in a 200 mm wafer silicon technology. We developed a technology process that enables fabrication with high yields of around 90%. Ge photodetectors with a Ge layer thickness of 450 nm and an area of 1600 µm2 (40 µm x 40 µm) show dark current densities of around 129 mA/cm2 and responsivities of 0.114 A/W measured by top illumination (TE polarization; λ = 1310 nm; angle of incidence = 14 °) at a reverse bias of 1 V. Nanohole arrays were structured in a 150 nm thick TiN layer. They were integrated into the back end of line and placed spatially close to the Ge photodetectors. After the metallization, passivation, and pad opening, the nanohole arrays were released with the help of an amorphous silicon stop layer. A significant impact of the TiN nanohole arrays on the optical behavior of the photodetector could be proven on the wafer level. Photocurrent measurements by top illumination confirm a strong dependence of optical properties on the polarization of the incident light and the nanohole array design. We demonstrate very stable photocurrents on the wafer level with a standard deviation of σ < 6%.
KW - plasmonics
KW - sensor
KW - nano hole array
Y1 - 2024
U6 - https://doi.org/10.1364/OE.530081
SN - 1094-4087
VL - 32
IS - 17
SP - 29099
EP - 29111
PB - Optica Publishing Group
ER -
TY - GEN
A1 - Dersch, Nadine
A1 - Roemer, Christian
A1 - Perez, Eduardo
A1 - Wenger, Christian
A1 - Schwarz, Mike
A1 - Iñíguez, Benjamín
A1 - Kloes, Alexander
T1 - Fast circuit simulation of memristive crossbar arrays with bimodal stochastic synaptic weights
T2 - 2024 IEEE Latin American Electron Devices Conference (LAEDC)
N2 - This paper presents an approach for highly efficient circuit simulation of hardware-based artificial neural networks by using memristive crossbar array architectures. There are already possibilities to test neural networks with stochastic weights via simulations like the macro model NeuroSim. However, the noise-based variability approach offers more realistic setting options including elements of a classical circuit simulation for more precise analysis of neural networks. With this approach, statistical parameter fluctuations can be simulated based on different distribution functions of devices. In Cadence Virtuoso, a simulation of a crossbar array with 10 synaptic weights following a bimodal distribution, the new approach shows a 1,000x speedup compared to a Monte Carlo simulation. Initial tests of a memristive crossbar array with over 15,000 stochastic weights to classify the MNIST dataset show that the new approach can be used to test the functionality of hardware-based neural networks.
KW - RRAM
Y1 - 2024
SN - 979-8-3503-6130-8
U6 - https://doi.org/10.1109/LAEDC61552.2024.10555829
SN - 979-8-3503-6129-2
SN - 2835-3471
SP - 1
EP - 4
PB - IEEE
ER -
TY - GEN
A1 - Reiter, Sebastian
A1 - Han, Weijia
A1 - Mai, Christian
A1 - Spirito, Davide
A1 - Jose, Josmy
A1 - Zöllner, Marvin Hartwig
A1 - Fursenko, Oksana
A1 - Schubert, Markus Andreas
A1 - Stemmler, Ivo
A1 - Wenger, Christian
A1 - Fischer, Inga Anita
T1 - Titanium Nitride Plasmonic Nanohole Arrays for CMOS-compatible integrated refractive index sensing: influence of layer thickness on optical properties
T2 - Plasmonics
Y1 - 2023
U6 - https://doi.org/10.1007/s11468-023-01810-3
SN - 1557-1963
SP - 1
EP - 13
ER -
TY - GEN
A1 - Han, Weijia
A1 - Reiter, Sebastian
A1 - Schlipf, Jon
A1 - Mai, Christian
A1 - Spirito, Davide
A1 - Jose, Josmy
A1 - Wenger, Christian
A1 - Fischer, Inga Anita
T1 - Strongly enhanced sensitivities of CMOS compatible plasmonic titanium nitride nanohole arrays for refractive index sensing under oblique incidence
T2 - Optics Express
N2 - Titanium nitride (TiN) is a complementary metal-oxide-semiconductor (CMOS) compatible material with large potential for the fabrication of plasmonic structures suited for device integration. However, the comparatively large optical losses can be detrimental for application. This work reports a CMOS compatible TiN nanohole array (NHA) on top of a multilayer stack for potential use in integrated refractive index sensing with high sensitivities at wavelengths between 800 and 1500 nm. The stack, consisting of the TiN NHA on a silicon dioxide (SiO2) layer with Si as substrate (TiN NHA/SiO2/Si), is prepared using an industrial CMOS compatible process. The TiN NHA/SiO2/Si shows Fano resonances in reflectance spectra under oblique excitation, which are well reproduced by simulation using both finite difference time domain (FDTD) and rigorous coupled-wave analysis (RCWA) methods. The sensitivities derived from spectroscopic characterizations increase with the increasing incident angle and match well with the simulated sensitivities. Our systematic simulation-based investigation of the sensitivity of the TiN NHA/SiO2/Si stack under varied conditions reveals that very large sensitivities up to 2305 nm per refractive index unit (nm RIU−1) are predicted when the refractive index of superstrate is similar to that of the SiO2 layer. We analyze in detail how the interplay between plasmonic and photonic resonances such as surface plasmon polaritons (SPPs), localized surface plasmon resonances (LSPRs), Rayleigh Anomalies (RAs), and photonic microcavity modes (Fabry-Pérot resonances) contributes to this result. This work not only reveals the tunability of TiN nanostructures for plasmonic applications but also paves the way to explore efficient devices for sensing in broad conditions.
KW - TiN
KW - Plasmonics
Y1 - 2023
U6 - https://doi.org/10.1364/OE.481993
SN - 1094-4087
VL - 31
IS - 11
SP - 17389
EP - 17407
ER -
TY - GEN
A1 - Dersch, Nadine
A1 - Perez-Bosch Quesada, Emilio
A1 - Pérez, Eduardo
A1 - Wenger, Christian
A1 - Roemer, Christian
A1 - Schwarz, Mike
A1 - Kloes, Alexander
T1 - Efficient circuit simulation of a memristive crossbar array with synaptic weight variability
T2 - Solid State Electronics
N2 - In this paper, we present a method for highly-efficient circuit simulation of a hardware-based artificial neural network realized in a memristive crossbar array. The statistical variability of the devices is considered by a noise-based simulation technique. For the simulation of a crossbar array with 8 synaptic weights in Cadence Virtuoso the new approach shows a more than 200x speed improvement compared to a Monte Carlo approach, yielding the same results. In addition, first results of an ANN with more than 15,000 memristive devices classifying test data of the MNIST dataset are shown, for which the speed improvement is expected to be several orders of magnitude. Furthermore, the influence on the classification of parasitic resistances of the connection lines in the crossbar is shown.
KW - RRAM
KW - Neural network
Y1 - 2023
U6 - https://doi.org/10.1016/j.sse.2023.108760
SN - 0038-1101
VL - 209
ER -
TY - GEN
A1 - Reiter, Sebastian
A1 - Ratzke, Markus
A1 - Nitsch, Paul-Gregor
A1 - Mai, Christian
A1 - Spirito, Davide
A1 - Corley-Wiciak, Agnieszka Anna
A1 - Wenger, Christian
A1 - Fischer, Inga A.
T1 - Optical response of titanium nitride plasmonic nanohole arrays : impact of square and hexagonal array geometry, pitch, and nanohole diameter
T2 - Plasmonics
N2 - Plasmonic nanohole arrays (NHAs) exhibit extraordinary optical transmission (EOT) evoked by resonant excitation of surface plasmons at an excitation wavelength, which is highly sensitive to changes in refractive index in the surrounding dielectric. This can enable the use of plasmonic NHAs in on-chip refractive index sensors. Such sensors can be realized on the cost-effective silicon platform by the integration of a plasmonic NHA and a Ge photodetector, provided that complementary metal–oxide–semiconductor (CMOS)-compatible materials are used for their fabrication. Titanium nitride (TiN) as a biocompatible and CMOS-compatible plasmonic transition metal nitride is well-suited for integration on the silicon platform; however, the comparatively large losses within the material require geometry optimization strategies in order to improve the optical properties of TiN NHAs for sensing. In this work, we investigated different TiN NHA geometries both in experiment and simulation. We extensively characterized square and hexagonal arrays with varying pitches and nanohole diameters and provide a detailed comparison of their optical properties. We also discuss characterization results for surface refractive index changes imposed by depositing a thin Al2O3 layer on top of the NHAs. While we do not observe a clear advantage of hexagonal arrays compared to square arrays for sensing, our results highlight the importance of geometry optimization for TiN NHAs integrated with devices.
KW - Plasmonic nanohole array
KW - Titanium nitride
KW - Hexagonal array
KW - Square array
KW - Nanohole diameters
Y1 - 2025
UR - https://link.springer.com/article/10.1007/s11468-025-02934-4
U6 - https://doi.org/10.1007/s11468-025-02934-4
VL - 20
SP - 8825
EP - 8834
PB - Springer
CY - New York, NY
ER -
TY - GEN
A1 - Lupina, Grzegorz
A1 - Dabrowski, Jarek Marek
A1 - Formanek, Peter
A1 - Schmeißer, Dieter
A1 - Sorge, Roland
A1 - Wenger, Christian
A1 - Zaumseil, Peter
A1 - Müssig, Hans-Joachim
T1 - Solid-state reaction between Pr and SiO2 studied by photoelectron spectroscopy and ab initio calculations
T2 - Materials Science in Semiconductor Processing
N2 - We report on the structural and electrical properties of Pr-based high-k dielectric films fabricated by solid-state reaction between metallic Pr and SiO2 underlayers. A non-destructive depth profiling using synchrotron radiation excited photoelectron spectroscopy (SR-PES), X-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM) were employed to examine the chemical composition and microstructure. Ab initio calculations were done to gain insight into the physical processes involved. SR-PES results indicate that Pr deposition at room temperature (RT) leads to the formation of a Pr silicide and a Pr oxide, what is in good agreement with the scenario expected from ab initio calculations. As revealed by TEM and electrical measurements, oxidation of the reacted structures, followed by annealing, results in a stacked dielectric composed of a SiO2-based buffer with an enhanced permittivity and a Pr silicate film with a high dielectric constant. The leakage current density of 10-4 A/cm2 was measured for stacks with capacitance equivalent thickness (CET) of 1.5 nm prepared by evaporation of the Pr layer on a 1.8 nm SiO2 film, followed by oxidation in air ambient and annealing in N2 atmosphere. The capacitance-voltage (C-V) curves exhibit a large flatband voltage (VFB) shift indicating the presence of a positive charge in the stack. Switching away from the Al contacts to Au gate electrodes introduces a significant reduction of the VFB by 1.3 eV, what is much more than the change expected from the work function difference between Al and Au (not, vert, similar0.9 eV). This in turn implies that VFB is strongly affected by the gate interface electrode.
KW - High-k dielectrics
KW - Photoelectron spectroscopy
KW - Interface reaction
Y1 - 2004
SN - 1369-8001
VL - 7
IS - 4-6
SP - 215
EP - 220
ER -
TY - GEN
A1 - Müssig, Hans-Joachim
A1 - Dabrowski, Jarek Marek
A1 - Wenger, Christian
A1 - Lupina, Grzegorz
A1 - Sorge, Roland
A1 - Formanek, Peter
A1 - Zaumseil, Peter
A1 - Schmeißer, Dieter
T1 - Ultrathin Dielectric Films Grown by Solid Phase Reaction of Pr with SiO2
T2 - MRS Proceedings
Y1 - 2004
SN - 1946-4274
VL - 811
ER -
TY - JOUR
A1 - Sohal, Rakesh
A1 - Lupina, Grzegorz
A1 - Lippert, Gunther
A1 - Wenger, Christian
A1 - Seifarth, Olaf
A1 - Schröder, Thomas
A1 - Tallarida, Massimo
A1 - Schmeißer, Dieter
T1 - Interface chemistry of high-k PrxAl2-xO3 (x=2-0) dielectrics on TiN for dynamic random access memory applications
KW - high-k
KW - dielectric
KW - random
Y1 - 2008
ER -
TY - GEN
A1 - Dirkmann, Sven
A1 - Kaiser, Jan
A1 - Wenger, Christian
A1 - Mussenbrock, Thomas
T1 - Filament Growth and Resistive Switching in Hafnium Oxide Memristive Devices
T2 - Plasma Sources Science and Technology
Y1 - 2018
U6 - https://doi.org/10.1021/acsami.7b19836
SN - 1361-6595
SN - 0963-0252
VL - 10
IS - 17
SP - 14857
EP - 14868
ER -
TY - GEN
A1 - Romero-Zaliz, Rocío
A1 - Pérez, Eduardo
A1 - Jimenez-Molinos, Francisco
A1 - Wenger, Christian
A1 - Roldan, Juan Bautista
T1 - Study of Quantized Hardware Deep Neural Networks Based on Resistive Switching Devices, Conventional versus Convolutional Approaches
T2 - Electronics (MDPI)
N2 - A comprehensive analysis of two types of artificial neural networks (ANN) is performed to assess the influence of quantization on the synaptic weights. Conventional multilayer-perceptron (MLP) and convolutional neural networks (CNN) have been considered by changing their features in the training and inference contexts, such as number of levels in the quantization process, the number of hidden layers on the network topology, the number of neurons per hidden layer, the image databases, the number of convolutional layers, etc. A reference technology based on 1T1R structures with bipolar memristors including HfO2 dielectrics was employed, accounting for different multilevel schemes and the corresponding conductance quantization algorithms. The accuracy of the image recognition processes was studied in depth. This type of studies are essential prior to hardware implementation of neural networks. The obtained results support the use of CNNs for image domains. This is linked to the role played by convolutional layers at extracting image features and reducing the data complexity. In this case, the number of synaptic weights can be reduced in comparison to conventional MLPs.
KW - RRAM
KW - resistive switching
KW - neural network
Y1 - 2021
U6 - https://doi.org/10.3390/electronics10030346
SN - 2079-9292
VL - 10
IS - 3
ER -
TY - GEN
A1 - Soltani Zarrin, Pouya
A1 - Zahari, Finn
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Pérez, Eduardo
A1 - Kohlstedt, Hermann
A1 - Wenger, Christian
T1 - Neuromorphic on‑chip recognition of saliva samples of COPD and healthy controls using memristive devices
T2 - Scientific Reports
N2 - Chronic Obstructive Pulmonary Disease (COPD) is a life-threatening lung disease, affecting millions of people worldwide. Implementation of Machine Learning (ML) techniques is crucial for the effective management of COPD in home-care environments. However, shortcomings of cloud-based ML tools in terms of data safety and energy efficiency limit their integration with low-power medical devices. To address this, energy efficient neuromorphic platforms can be used for the hardware-based implementation of ML methods. Therefore, a memristive neuromorphic platform is presented in this paper for the on-chip recognition of saliva samples of COPD patients and healthy controls. The results of its performance evaluations showed that the digital neuromorphic chip is capable of recognizing unseen COPD samples with accuracy and sensitivity values of 89% and 86%, respectively. Integration of this technology into personalized healthcare devices will enable the better management of chronic diseases such as COPD.
KW - RRAM
KW - memristive device
KW - neural network
Y1 - 2020
U6 - https://doi.org/10.1038/s41598-020-76823-7
SN - 2045-2322
VL - 10
ER -
TY - GEN
A1 - Soltani Zarrin, Pouya
A1 - Rockendorf, Niels
A1 - Wenger, Christian
T1 - In-Vitro Classification of Saliva Samples of COPD Patients and Healthy Controls Using Machine Learning Tools
T2 - IEEE Access
N2 - Chronic Obstructive Pulmonary Disease (COPD) is a life-threatening lung disease and a major cause of morbidity and mortality worldwide. Although a curative therapy has yet to be found, permanent monitoring of biomarkers that reflect the disease progression plays a pivotal role for the effective management of COPD. The accurate examination of respiratory tract fluids like saliva is a promising approach for staging the disease and predicting its upcoming exacerbations in a Point-of-Care (PoC) environment. Nonetheless, this approach is only feasible by concurrent consideration of patients' demographic and medical parameters. Therefore, Machine Learning (ML) tools are necessary for the comprehensive recognition of COPD in a PoC setting. As a result, the objective of this work was to implement ML tools on the data acquired from characterizing saliva samples of COPD patients and healthy controls for classification purposes. First, a permittivity biosensor was used to characterize dielectric properties of saliva samples and, subsequently, ML tools were applied on the acquired data for classification. The XGBoost gradient boosting algorithm provided a high classification accuracy of 91.25%, making it a promising model for COPD recognition. Integration of this model on a neuromorphic chip, in the future, will enable the real-time detection of COPD in PoC, with low energy consumption and high patient privacy.
KW - COPD
KW - Machine learning
KW - Point of care
Y1 - 2020
U6 - https://doi.org/10.1109/ACCESS.2020.3023971
SN - 2169-3536
VL - Vol. 8
SP - 168053
EP - 168060
ER -
TY - GEN
A1 - Soltani Zarrin, Pouya
A1 - Wenger, Christian
T1 - Implementation of Siamese-Based Few-Shot Learning Algorithms for the Distinction of COPD and Asthma Subjects
T2 - Artificial Neural Networks and Machine Learning – ICANN 2020 : 29th International Conference on Artificial Neural Networks, Bratislava, Slovakia, September 15–18, 2020, Proceedings, Part I
N2 - This paper investigates the practicality of applying braininspired Few-Shot Learning (FSL) algorithms for addressing shortcomings of Machine Learning (ML) methods in medicine with limited data availability. As a proof of concept, the application of ML for the detection of Chronic Obstructive Pulmonary Disease (COPD) patients was investigated. The complexities associated with the distinction of COPD and asthma patients and the lack of sufficient training data for asthma subjects impair the performance of conventional ML models for the recognition of COPD. Therefore, the objective of this study was to implement FSL methods for the distinction of COPD and asthma subjects with a few available data points. The proposed FSL models in this work were capable of recognizing asthma and COPD patients with 100% accuracy, demonstrating the feasibility of the approach for applications such as medicine with insufficient data availability.
KW - Machine Learning
KW - COPD
Y1 - 2020
U6 - https://doi.org/10.1007/978-3-030-61609-0_34
SP - 431
EP - 440
PB - Springer
CY - Cham
ER -
TY - GEN
A1 - Zanotti, Tommaso
A1 - Puglisi, Francesco Maria
A1 - Milo, Valerio
A1 - Pérez, Eduardo
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Ossorio, Óscar G.
A1 - Wenger, Christian
A1 - Pavan, Paolo
A1 - Olivo, Piero
A1 - Ielmini, Daniele
T1 - Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays
T2 - IEEE Transactions on Electron Devices
N2 - Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25- μm BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.
KW - RRAM
KW - in-memory computing
KW - HfO2
Y1 - 2020
U6 - https://doi.org/10.1109/TED.2020.3025271
SN - 0018-9383
SN - 1557-9646
VL - 67
IS - 11
SP - 4611
EP - 4615
ER -
TY - GEN
A1 - Zahari, Finn
A1 - Pérez, Eduardo
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Kohlstedt, Hermann
A1 - Wenger, Christian
A1 - Ziegler, Martin
T1 - Analogue pattern recognition with stochastic switching binary CMOS‑integrated memristive devices
T2 - Scientific Reports
N2 - Biological neural networks outperform todays computer technology in terms of power consumption and computing speed when associative tasks, like pattern recognition, are to be solved. The analogue and massive parallel in-memory computing in biology differs strongly with conventional transistor electronics using the von Neumann architecture. Therefore, novel bio-inspired computing architectures are recently highly investigated in the area of neuromorphic computing. Here, memristive devices, which serve as non-volatile resistive memory, are used to emulate the plastic behaviour of biological synapses. In particular, CMOS integrated resistive random access memory (RRAM) devices are promising candidates to extend conventional CMOS technology in neuromorphic systems. However, dealing with the inherent stochasticity of the resistive switching effect can be challenging for network performance. In this work, the probabilistic switching is exploited to emulate stochastic plasticity with fully CMOS integrated binary RRAM devices. Two different RRAM technologies with different device variabilities are investigated in detail and their use in a stochastic artificial neural network (StochANN) to solve the MINST pattern recognition task is examined. A mixed-signal implementation with hardware synapses and software neurons as well as numerical simulations show the proposed concept of stochastic computing is able to handle analogue data with binary memory cells.
KW - RRAM
KW - memristive device
KW - neural network
KW - HfO2
Y1 - 2020
U6 - https://doi.org/10.1038/s41598-020-71334-x
SN - 2045-2322
VL - 10
ER -
TY - GEN
A1 - Petzold, Stefan
A1 - Piros, Eszter
A1 - Eilhardt, Robert
A1 - Zintler, Alexander
A1 - Vogel, Tobias
A1 - Kaiser, Nico
A1 - Radetinac, Aldin
A1 - Komissinskiy, Philipp
A1 - Jalaguier, Eric
A1 - Nolot, Emmanuel
A1 - Charpin-Nicolle, Christelle
A1 - Wenger, Christian
A1 - Molina-Luna, Leopoldo
A1 - Miranda, Enrique
A1 - Alff, Lambert
T1 - Tailoring the Switching Dynamics in Yttrium Oxide-Based RRAM Devices by Oxygen Engineering: From Digital to Multi-Level Quantization toward Analog Switching
T2 - Advanced Electronic Materials
N2 - This work investigates the transition from digital to gradual or analog resistive switching in yttrium oxide‐based resistive random‐access memory devices. It is shown that this transition is determined by the amount of oxygen in the functional layer. A homogeneous reduction of the oxygen content not only reduces the electroforming voltage, allowing for forming‐free devices, but also decreases the voltage operation window of switching, thereby reducing intra‐device variability. The most important effect as the dielectric becomes substoichiometric by oxygen engineering is that more intermediate (quantized) conduction states are accessible. A key factor for this reproducibly controllable behavior is the reduced local heat dissipation in the filament region due to the increased thermal conductivity of the oxygen depleted layer. The improved accessibility of quantized resistance states results in a semi‐gradual switching both for the set and reset processes, as strongly desired for multi‐bit storage and for an accurate definition of the synaptic weights in neuromorphic systems. A theoretical model based on the physics of mesoscopic structures describing current transport through a nano‐constriction including asymmetric potential drops at the electrodes and non‐linear conductance quantization is provided. The results contribute to a deeper understanding on how to tailor materials properties for novel memristive functionalities.
KW - RRAM
KW - Multilevel switching
Y1 - 2020
U6 - https://doi.org/10.1002/aelm.202000439
SN - 2199-160X
VL - 6
IS - 11
ER -
TY - GEN
A1 - Perez-Avila, Antonio Javier
A1 - Gonzalez-Cordero, Gerardo
A1 - Pérez, Eduardo
A1 - Perez-Bosch Quesada, Emilio
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Wenger, Christian
A1 - Roldan, Juan Bautista
A1 - Jimenez-Molinos, Francisco
T1 - Behavioral modeling of multilevel HfO2-based memristors for neuromorphic circuit simulation
T2 - XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain
N2 - An artificial neural network based on resistive switching memristors is implemented and simulated in LTspice. The influence of memristor variability and the reduction of the continuous range of synaptic weights into a discrete set of conductance levels is analyzed. To do so, a behavioral model is proposed for multilevel resistive switching memristors based on Al-doped HfO2 dielectrics, and it is implemented in a spice based circuit simulator. The model provides an accurate description of the conductance in the different conductive states in addition to describe the device-to-device variability
KW - RRAM
KW - Multilevel switching
KW - behavorial model
Y1 - 2020
U6 - https://doi.org/10.1109/DCIS51330.2020.9268652
ER -
TY - GEN
A1 - Pérez, Eduardo
A1 - Ossorio, Óscar G.
A1 - Dueñas, Salvador
A1 - Castán, Helena
A1 - García, Hector
A1 - Wenger, Christian
T1 - Programming Pulse Width Assessment for Reliable and Low-Energy Endurance Performance in Al:HfO2-Based RRAM Arrays
T2 - Electronics (MDPI)
N2 - A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 μ s and 50 ns and assessed on Al-doped HfO 2 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 μ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 μ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width
KW - RRAM
KW - Reliability
Y1 - 2020
U6 - https://doi.org/10.3390/electronics9050864
SN - 2079-9292
VL - 9
IS - 5
ER -
TY - GEN
A1 - Morales, Carlos
A1 - Mahmoodinezhad, Ali
A1 - Schubert, Andreas Markus
A1 - Wenger, Christian
A1 - Henkel, Karsten
A1 - Flege, Jan Ingo
T1 - Functional ultra-thin oxide films deposited by atomic layer deposition on structured substrates
T2 - Verhandlungen der DPG - SurfaceScience21
N2 - In the last decades, atomic layer deposition (ALD) has gained prominence in the materials and surface science communities owing to its high potential for integration as a scalable process in microelectronics. ALD's largest strengths are its well-controlled layer-by-layer deposition and growth conformity on 3D structures. Yet, the ALD technique is also well known to lead to amorphous and defective, non-stoichiometric thin films, resulting in modified materials properties that may even preferentially be used in certain applications. To study these issues, we have developed an in-situ ALD reactor attached to an X-ray photoelectron spectroscopy (XPS) system, capable of switching between both pump and flow-type operation. This novel tool allows to cover the entire range of compounds and recipes used in ALD, thus clarifying the role of such defects at different deposition stages, growth conditions and film/substrate interfaces. To exemplify these sorts of studies, we show the deposition of Al2O3 5-10 nm films on nanostructured Si, and their use as substrates for functional CeOx ALD deposits.
KW - Atomic layer deposition
KW - sensors
KW - structured substrates
KW - in-situ X-ray photoelectron spectroscopy
Y1 - 2021
UR - https://www.dpg-verhandlungen.de/year/2021/conference/surfacescience/part/o/session/74/contribution/5
VL - 2021
PB - Deutsche Physikalische Gesellschaft e.V.
CY - Bad Honnef
ER -
TY - GEN
A1 - Pérez-Bosch Quesada, Emilio
A1 - Romero-Zaliz, Rocío
A1 - Pérez, Eduardo
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Reuben, John
A1 - Schubert, Markus Andreas
A1 - Jiménez-Molinos, Francisco
A1 - Roldán, Juan Bautista
A1 - Wenger, Christian
T1 - Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems
T2 - Electronics (MDPI)
N2 - In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of
experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance
levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.
KW - RRAM
KW - multilevel switching
KW - compact modeling
KW - Verilog-A
Y1 - 2021
U6 - https://doi.org/10.3390/electronics10060645
SN - 2079-9292
VL - 10
IS - 6
ER -
TY - GEN
A1 - Pechmann, Stefan
A1 - Mai, Timo
A1 - Völkel, Matthias
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Pérez, Eduardo
A1 - Perez-Bosch Quesada, Emilio
A1 - Reichenbach, Marc
A1 - Wenger, Christian
A1 - Hagelauer, Amelie
T1 - A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells
T2 - Electronics
N2 - In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage
pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.
KW - RRAM
KW - Multilevel switching
KW - Programming circuit
Y1 - 2021
U6 - https://doi.org/10.3390/electronics10050530
SN - 2079-9292
VL - 10
IS - 5
ER -
TY - GEN
A1 - Matbaechi Ettehad, Honeyeh
A1 - Wenger, Christian
T1 - Characterization and Separation of Live and Dead Yeast Cells Using CMOS-Based DEP Microfluidics
T2 - Micromachines
N2 - This study aims at developing a miniaturized CMOS integrated silicon-based microfluidic system, compatible with a standard CMOS process, to enable the characterization, and separation of live and dead yeast cells (as model bio-particle organisms) in a cell mixture using the DEP technique. DEP offers excellent benefits in terms of cost, operational power, and especially easy electrode integration with the CMOS architecture, and requiring label-free sample preparation. This can increase the likeliness of using DEP in practical settings. In this work the DEP force was generated using an interdigitated electrode arrays (IDEs) placed on the bottom of a CMOS-based silicon
microfluidic channel. This system was primarily used for the immobilization of yeast cells using DEP. This study validated the system for cell separation applications based on the distinct responses of live and dead cells and their surrounding media. The findings confirmed the device’s capability for efficient, rapid and selective cell separation. The viability of this CMOS embedded microfluidic for dielectrophoretic cell manipulation applications and compatibility of the dielectrophoretic structure with CMOS production line and electronics, enabling its future commercially mass production.
KW - dielectrophoresis
KW - microfluidics
KW - cell characterization
KW - CMOS
Y1 - 2021
U6 - https://doi.org/10.3390/mi12030270
SN - 2072-666X
VL - 12
IS - 3
ER -
TY - GEN
A1 - Pérez, Eduardo
A1 - Pérez-Ávila, Antonio Javier
A1 - Romero-Zaliz, Rocío
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Pérez-Bosch Quesada, Emilio
A1 - Roldan, Juan Bautista
A1 - Jiménez-Molinos, Francisco
A1 - Wenger, Christian
T1 - Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing
T2 - Electronics (MDPI)
N2 - Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8×8 vector-matrixmultiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters.
KW - RRAM
KW - Multilevel switching
KW - In-memory computing
Y1 - 2021
U6 - https://doi.org/10.3390/electronics10091084
SN - 2079-9292
VL - 10
IS - 9
ER -
TY - GEN
A1 - Milo, Valerio
A1 - Anzalone, Francesco
A1 - Zambelli, Cristian
A1 - Pérez, Eduardo
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Ossorio, Óscar G.
A1 - Olivo, Piero
A1 - Wenger, Christian
A1 - Ielmini, Daniele
T1 - Optimized programming algorithms for multilevel RRAM in hardware neural networks
T2 - IEEE International Reliability Physics Symposium (IRPS), 2021
N2 - A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO 2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5% (vs. software 93.27%) in MNIST recognition.
KW - RRAM
KW - Multilevel switching
KW - neural network
KW - memristive switching
Y1 - 2021
SN - 978-1-7281-6894-4
U6 - https://doi.org/10.1109/IRPS46558.2021.9405119
SN - 1938-1891
ER -
TY - GEN
A1 - Petryk, Dmytro
A1 - Dyka, Zoya
A1 - Pérez, Eduardo
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Kabin, Ievgen
A1 - Wenger, Christian
A1 - Langendörfer, Peter
T1 - Evaluation of the Sensitivity of RRAM Cells to Optical Fault Injection Attacks
T2 - EUROMICRO Conference on Digital System Design (DSD 2020), Special Session: Architecture and Hardware for Security Applications (AHSA)
Y1 - 2021
SN - 978-1-7281-9535-3
U6 - https://doi.org/10.1109/DSD51259.2020.00047
SN - 978-1-7281-9536-0
ER -
TY - GEN
A1 - Romero-Zaliz, Rocío
A1 - Pérez, Eduardo
A1 - Jimenez-Molinos, Francisco
A1 - Wenger, Christian
A1 - Roldan, Juan Bautista
T1 - Influence of variability on the performance of HfO2 memristor-based convolutional neural networks
T2 - Solid State Electronics
N2 - A study of convolutional neural networks (CNNs) was performed to analyze the influence of quantization and variability in the network synaptic weights. Different CNNs were considered accounting for the number of convolutional layers, size of the filters in the convolutional layer, number of neurons in the final network layers and different sets of quantization levels. The conductance levels of fabricated 1T1R structures based on HfO2 memristors were considered as reference for four or eight level quantization processes at the inference stage of the CNNs, which were previous trained with the MNIST dataset. We also included the variability of the experimental conductance levels that was found to be Gaussian distributed and was correspondingly modeled for the synaptic weight implementation.
KW - RRAM
KW - neural network
KW - HfO2
KW - memristive switching
Y1 - 2021
U6 - https://doi.org/10.1016/j.sse.2021.108064
SN - 0038-1101
VL - 185
ER -
TY - GEN
A1 - Pérez, Eduardo
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Perez-Bosch Quesada, Emilio
A1 - Wenger, Christian
T1 - Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays
T2 - IEEE Transactions on Electron Devices
N2 - Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm
to employ should be based on the specific application targeted for the RRAM array.
KW - RRAM
KW - Multilevel switching
KW - HfO2
Y1 - 2021
U6 - https://doi.org/10.1109/TED.2021.3072868
SN - 0018-9383
SN - 1557-9646
VL - 68
IS - 6
SP - 2693
EP - 2698
ER -
TY - GEN
A1 - Ossorio, Óscar G.
A1 - Vinuesa, Guillermo
A1 - Garcia, Hector
A1 - Sahelices, Benjamin
A1 - Dueñas, Salvador
A1 - Castán, Helena
A1 - Pérez, Eduardo
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Wenger, Christian
T1 - Performance Assessment of Amorphous HfO2-based RRAM Devices for Neuromorphic Applications
T2 - ECS Transactions
N2 - The use of thin layers of amorphous hafnium oxide has been shown to be suitable for the manufacture of Resistive Random-Access memories (RRAM). These memories are of great interest because of their simple structure and non-volatile character. They are particularly appealing as they are good candidates for substituting flash memories. In this work, the performance of the MIM structure that takes part of a 4 kbit memory array based on 1-transistor-1-resistance (1T1R) cells was studied in terms of control of intermediate states and cycle durability. DC and small signal experiments were carried out in order to fully characterize the devices, which presented excellent multilevel capabilities and resistive-switching behavior.
KW - RRAM
KW - resistive switching
KW - HfO2
Y1 - 2021
U6 - https://doi.org/10.1149/10202.0029ecst
SN - 1938-6737
SN - 1938-5862
VL - 102
IS - 2
SP - 29
EP - 35
ER -
TY - GEN
A1 - Mahmoodinezhad, Ali
A1 - Morales, Carlos
A1 - Naumann, Franziska
A1 - Plate, Paul
A1 - Meyer, Robert
A1 - Janowitz, Christoph
A1 - Henkel, Karsten
A1 - Kot, Małgorzata
A1 - Zöllner, Marvin Hartwig
A1 - Wenger, Christian
A1 - Flege, Jan Ingo
T1 - Low-temperature atomic layer deposition of indium oxide thin films using trimethylindium and oxygen plasma
T2 - Journal of Vacuum Science and Technology A
N2 - Indium oxide (InxOy) thin films were deposited by plasma-enhanced atomic layer deposition (PEALD) using trimethylindium and oxygen plasma in a low-temperature range of 80–200 °C. The optical properties, chemical composition, crystallographic structure, and electrical characteristics of these layers were investigated by spectroscopic ellipsometry (SE), x-ray photoelectron spectroscopy (XPS), x-ray diffraction (XRD), as well as current-voltage and capacitance-voltage measurements. The SE results yielded a nearly constant growth rate of 0.56 Å per cycle and a thickness inhomogeneity of ≤1.2% across 4-in. substrates in the temperature range of 100–150 °C. The refractive index (at 632.8 nm) was found to be 2.07 for the films deposited at 150 °C. The PEALD-InxOy layers exhibit a direct (3.3 ± 0.2 eV) and an indirect (2.8 ± 0.1 eV) bandgap with an uptrend for both with increasing substrate temperature. Based on XPS characterization, all InxOy samples are free of carbon impurities and show a temperature-dependent off-stoichiometry indicating oxygen vacancies. XRD diffraction patterns demonstrate an onset of crystallization at 150 °C. Consistent with the optical, XPS, and XRD data, the films deposited at ≥150 °C possess higher electrical conductivity. Our findings prove that a low-temperature PEALD process of InxOy is feasible and promising for a high-quality thin-film deposition without chemical impurities on thermally fragile substrates.
KW - Indium oxide
KW - Plasma-enhanced atomic layer deposition
KW - X-ray photoelectron spectroscopy
KW - Ellipsometry
KW - X-ray diffraction
KW - Electrical properties
Y1 - 2021
U6 - https://doi.org/10.1116/6.0001375
SN - 0734-2101
SN - 1520-8559
VL - 39
IS - 6
ER -
TY - GEN
A1 - Yun, Min Ju
A1 - Lee, Doowon
A1 - Kim, Sungho
A1 - Wenger, Christian
A1 - Kim, Hee-Dong
T1 - A nonlinear resistive switching behaviors of Ni/HfO2/TiN memory structures for self-rectifying resistive switching memory
T2 - Materials Characterization
N2 - This work reports forming free/self-rectifying resistive switching characteristics and dependency of the top electrode (TE) of a crystalline HfO2-based resistive switching memory device. In the memory cells, nonlinear bipolar resistive switching characteristics, i.e., an asymmetric current-voltage curve like the Schottky diode, was
observed. In addition, the device exhibits resistive switching behaviors without forming process, which makes it possible to switch the resistance state under ultra-low current levels of <10 nA. In addition, compared to the resistive switching of the proposed resistive switching memory devices with different TEs, the VSET was decreased when using TE with lower work function, and the height read margin was obtained in the sample with the Ni TE, covering over 56 × 56 arrays. Consequently, these results indicate that the interface control resistive switching properties in memory structures having the Schottky junction warrant the realization of selector-free resistive
switching memory cells in a high-density crossbar array.
KW - RRAM
KW - resistive switching
KW - HfO2
Y1 - 2021
U6 - https://doi.org/10.1016/j.matchar.2021.111578
SN - 1044-5803
VL - 182
ER -
TY - GEN
A1 - Perez-Bosch Quesada, Emilio
A1 - Pérez, Eduardo
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Wenger, Christian
T1 - Memristive-based in-memory computing: from device to large-scale CMOS integration
T2 - Neuromorphic Computing and Engineering
N2 - With the rapid emergence of in-memory computing systems based on memristive technology, the integration of such memory devices in large-scale architectures is one of the main aspects to tackle.
In this work we present a study of HfO2-based memristive devices for their integration in large-scale CMOS systems, namely 200 mm wafers. The DC characteristics of single metal–insulator–metal
devices are analyzed taking under consideration device-to-device variabilities and switching properties. Furthermore, the distribution of the leakage current levels in the pristine state of the
samples are analyzed and correlated to the amount of formingless memristors found among the measured devices. Finally, the obtained results are fitted into a physic-based compact model that
enables their integration into larger-scale simulation environments.
KW - RRAM
KW - memristive device
KW - HfO2
Y1 - 2021
U6 - https://doi.org/10.1088/2634-4386/ac2cd4
SN - 2634-4386
VL - 1
IS - 2
ER -
TY - GEN
A1 - Baroni, Andrea
A1 - Zambelli, Cristian
A1 - Olivo, Piero
A1 - Pérez, Eduardo
A1 - Wenger, Christian
A1 - Ielmini, Daniele
T1 - Tackling the Low Conductance State Drift through Incremental Reset and Verify in RRAM Arrays
T2 - 2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021
N2 - Resistive switching memory (RRAM) is a promising technology for highly efficient computing scenarios. RRAM arrays enabled the acceleration of neural networks for artificial intelligence and the creation of In-Memory Computing circuits. However, the arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation in those applications. Among those, one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are fundamental for an accurate Multi-level conductance operation. In this work, we tackle the issue by developing an Incremental Reset and Verify technique showing enhanced variability and reliability features compared with a traditional refresh-based approach.
KW - RRAM
KW - resistive switching
KW - neural network
Y1 - 2021
SN - 978-1-6654-1794-5
SN - 978-1-6654-1795-2
U6 - https://doi.org/10.1109/IIRW53245.2021.9635613
SN - 2374-8036
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
TY - GEN
A1 - Romero-Zaliz, Rocio
A1 - Cantudo, Antonio
A1 - Pérez, Eduardo
A1 - Jimenez-Molinos, Francisco
A1 - Wenger, Christian
A1 - Roldan, Juan Bautista
T1 - An Analysis on the Architecture and the Size of Quantized Hardware Neural Networks Based on Memristors
T2 - Electronics (MDPI)
N2 - We have performed different simulation experiments in relation to hardware neural networks (NN) to analyze the role of the number of synapses for different NN architectures in the network accuracy, considering different datasets. A technology that stands upon 4-kbit 1T1R ReRAM arrays, where resistive switching devices based on HfO2 dielectrics are employed, is taken as a reference. In our study, fully dense (FdNN) and convolutional neural networks (CNN) were considered, where the NN size in terms of the number of synapses and of hidden layer neurons were varied. CNNs work better when the number of synapses to be used is limited. If quantized synaptic weights are included, we observed thatNNaccuracy decreases significantly as the number of synapses is reduced; in this respect, a trade-off between the number of synapses and the NN accuracy has to be achieved. Consequently, the CNN architecture must be carefully designed; in particular, it was noticed that different datasets need specific architectures according to their complexity to achieve good results. It was shown that due to the number of variables that can be changed in the optimization of a NN hardware implementation, a specific solution has to be worked in each case in terms of synaptic weight levels, NN architecture, etc.
KW - RRAM
KW - memristive device
KW - neural network
Y1 - 2021
U6 - https://doi.org/10.3390/electronics10243141
SN - 2079-9292
VL - 10
IS - 24
ER -
TY - GEN
A1 - Stanke, Sandra
A1 - Wenger, Christian
A1 - Bier, Frank F.
A1 - Hölzel, Ralph
T1 - AC electrokinetic immobilization of influenza virus
T2 - Electrophoresis
N2 - The use of alternating current (AC) electrokinetic forces, like dielectrophoresis and AC electroosmosis, as a simple and fast method to immobilize sub-micrometer objects onto nanoelectrode arrays is presented. Due to its medical relevance, the influenza virus is chosen as a model organism. One of the outstanding features is that the immobilization of viral material to the electrodes can be achieved permanently, allowing subsequent handling independently from the electrical setup. Thus, by using merely electric fields, we demonstrate that the need of prior chemical surface modification could become obsolete. The accumulation of viral material over time is observed by fluorescence microscopy. The influences of side effects like electrothermal fluid flow, causing a fluid motion above the electrodes and causing an intensity gradient within the electrode array, are discussed. Due to the improved resolution by combining fluorescence microscopy with deconvolution, it is shown that the viral material is mainly drawn to the electrode edge and to a lesser extent to the electrode surface. Finally, areas of application for this functionalization technique are presented.
KW - dielectrophoresis
KW - immobilization
KW - virus
Y1 - 2022
U6 - https://doi.org/10.1002/elps.202100324
SN - 1522-2683
VL - 43
IS - 12
SP - 1309
EP - 1321
ER -
TY - GEN
A1 - Bischoff, Carl
A1 - Leise, Jakob
A1 - Perez-Bosch Quesada, Emilio
A1 - Pérez, Eduardo
A1 - Wenger, Christian
A1 - Kloes, Alexander
T1 - Implementation of device-to-device and cycle-to-cycle variability of memristive devices in circuit simulations
T2 - Solid-State Electronics
N2 - We present a statistical procedure for the extraction of parameters of a compact model for memristive devices. Thereby, in a circuit simulation the typical fluctuations of the current–voltage (I-V) characteristics from device-to-device (D2D) and from cycle-to-cycle (C2C) can be emulated. The approach is based on the Stanford model
whose parameters play a key role to integrating D2D and C2C dispersion. The influence of such variabilities over the model’s parameters is investigated by using a fitting algorithm fed with experimental data. After this, the statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of RRAM cells or memristor-based artificial neural networks.
KW - RRAM
KW - circuit simulation
KW - HfO2
Y1 - 2022
U6 - https://doi.org/10.1016/j.sse.2022.108321
SN - 0038-1101
VL - 194
ER -
TY - GEN
A1 - Mannocci, Piergiulio
A1 - Baroni, Andrea
A1 - Melacarne, Enrico
A1 - Zambelli, Cristian
A1 - Olivo, Piero
A1 - Pérez, Eduardo
A1 - Wenger, Christian
A1 - Ielmini, Daniele
T1 - In-Memory Principal Component Analysis by Crosspoint Array of Rresistive Switching Memory
T2 - IEEE Nanotechnology Magazine
N2 - In Memory Computing (IMC) is one of the most promising candidates
for data-intensive computing accelerators of machine learning (ML). A key ML algorithm for dimensionality reduction and classification is principal component analysis (PCA), which heavily relies on matrixvector multiplications (MVM) for which classic von Neumann architectures are not optimized. Here, we provide the experimental
demonstration of a new IMCbased PCA algorithm based on power iteration and deflation executed in a 4-kbit array of resistive switching random-access memory (RRAM). The classification accuracy of the Wisconsin Breast Cancer data set reaches 95.43%, close to floatingpoint implementation. Our simulations indicate a 250× improvement in energy efficiency compared to commercial GPUs, thus supporting IMC for energy-efficient ML in modern data-intensive computing.
KW - RRAM
KW - Multilevel switching
KW - neural network
Y1 - 2022
U6 - https://doi.org/10.1109/MNANO.2022.3141515
SN - 1932-4510
VL - 16
IS - 2
SP - 4
EP - 13
ER -
TY - GEN
A1 - Strobel, Carsten
A1 - Alvarado Chavarin, Carlos
A1 - Leszczynski, Sebastian
A1 - Richter, Karola
A1 - Knaut, Martin
A1 - Reif, Johanna
A1 - Völkel, Sandra
A1 - Albert, Matthias
A1 - Wenger, Christian
A1 - Bartha, Johann Wolfgang
A1 - Mikolajick, Thomas
T1 - Improved Graphene-base Heterojunction Transistor with Different Collector Semi-conductors for High-frequency Applications
T2 - Advanced Materials Letters
N2 - A new kind of transistor device with a graphene monolayer embedded between two n-type silicon layers is fabricated and characterized. The device is called graphene-base heterojunction transistor (GBHT). The base-voltage controls the current of the device flowing from the emitter via graphene to the collector. The transit time for electrons passing by the ultrathin graphene layer is extremely short which makes the device very promising for high frequency RF-electronics. The output current of the device is saturated and clearly modulated by the base voltage. Further, the silicon collector of the GBHT is replaced by germanium to improve the device performance. This enabled the collector current to be increased by almost three orders of magnitude. Also, the common-emitter current gain (Ic/Ib) increased from 10-3 to approximately 0.3 for the newly designed device. However, the ON-OFF ratio of the improved germanium based GBHT has so far been rather low. Further optimizations are necessary in order to fully exploit the potential of the graphene-base heterojunction transistor.
KW - Graphene
KW - transistor
Y1 - 2022
U6 - https://doi.org/10.5185/amlett.2022.011688
SN - 0976-3961
VL - 13
IS - 1
ER -
TY - GEN
A1 - Fritscher, Markus
A1 - Knödtel, Johannes
A1 - Mallah, Maen
A1 - Pechmann, Stefan
A1 - Perez-Bosch Quesada, Emilio
A1 - Rizzi, Tommaso
A1 - Wenger, Christian
A1 - Reichenbach, Marc
T1 - Mitigating the Effects of RRAM Process Variation on the Accuracy of Artifical Neural Networks
T2 - Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science
N2 - Weight storage is a key challenge in the efficient implementation of artificial neural networks. Novel memory technologies such as RRAM are able to greatly improve density and introduce non-volatility and multibit capabilities to this component of ANN accelerators. The usage of RRAM in this domain comes with downsides, mainly caused by cycle-to-cycle and device-to-device variability leading to erroneous readouts, greatly affecting digital systems. ANNs have the ability to compensate for this by their inherent redundancy and usually exhibit a gradual deterioration in the accuracy of the task at hand. This means, that slight error rates can be acceptable for weight storage in an ANN accelerator. In this work we link device-to-device variability to the accuracy of an ANN for such an accelerator. From this study, we can estimate how strongly a certain net is affected by a certain device parameter variability. This methodology is then used to present three mitigation strategies and to evaluate how they affect the reaction of the network to variability: a) Dropout Layers b) Fault-Aware Training c) Redundancy. These mitigations are then evaluated by their ability to improve accuracy and to lower hardware overhead by providing data for a real-word example. We improved this network’s resilience in such a way that it could tolerate double the variation in one of the device parameters (standard deviation of the oxide thickness can be 0.4 nm instead of 0.2 nm while maintaining sufficient accuracy.)
KW - RRAM
KW - memristive device
KW - neural network
Y1 - 2022
SN - 978-3-031-04579-0
SN - 978-3-031-04580-6
U6 - https://doi.org/10.1007/978-3-031-04580-6_27
SN - 0302-9743
SN - 1611-3349
SP - 401
EP - 417
PB - Springer
ER -
TY - GEN
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Pérez, Eduardo
A1 - Lisker, Marco
A1 - Schubert, Markus Andreas
A1 - Perez-Bosch Quesada, Emilio
A1 - Wenger, Christian
A1 - Mai, Andreas
T1 - Modulating the Filamentary-Based Resistive Switching Properties of HfO2 Memristive Devices by Adding Al2O3 Layers
T2 - Electronics : open access journal
N2 - The resistive switching properties of HfO2 based 1T-1R memristive devices are electrically modified by adding ultra-thin layers of Al2O3
into the memristive device. Three different types of memristive stacks are fabricated in the 130 nm CMOS technology of IHP. The switching properties of the memristive devices are discussed with respect to forming voltages, low resistance state and high resistance state characteristics and their variabilities. The experimental I–V characteristics of set and reset operations are evaluated by using the quantum point contact model. The properties of the conduction filament in the on and off states of the memristive devices are discussed with respect to the model parameters obtained from the QPC fit.
KW - RRAM
KW - HfO2
KW - filamentary switching
Y1 - 2022
U6 - https://doi.org/10.3390/electronics11101540
SN - 2079-9292
VL - 11
IS - 10
ER -
TY - GEN
A1 - Glukhov, Artem
A1 - Milo, Valerio
A1 - Baroni, Andrea
A1 - Lepri, Nicola
A1 - Zambelli, Cristian
A1 - Olivo, Piero
A1 - Pérez, Eduardo
A1 - Wenger, Christian
A1 - Ielmini, Daniele
T1 - Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators
T2 - 2022 IEEE International Reliability Physics Symposium (IRPS)
N2 - Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators.
KW - RRAM
KW - Multilevel switching
KW - neural network
Y1 - 2022
SN - 978-1-6654-7950-9
SN - 978-1-6654-7951-6
U6 - https://doi.org/10.1109/IRPS48227.2022.9764497
SN - 2473-2001
SP - 3C.3-1
EP - 3C.3-7
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
TY - GEN
A1 - Janowitz, Christoph
A1 - Mahmoodinezhad, Ali
A1 - Kot, Małgorzata
A1 - Morales, Carlos
A1 - Naumann, Franziska
A1 - Plate, Paul
A1 - Zöllner, Marvin Hartwig
A1 - Bärwolf, Florian
A1 - Stolarek, David
A1 - Wenger, Christian
A1 - Henkel, Karsten
A1 - Flege, Jan Ingo
T1 - Toward controlling the Al2O3/ZnO interface properties by in situ ALD preparation
T2 - Dalton Transactions
N2 - An Al2O3/ZnO heterojunction was grown on a Si single crystal substrate by subsequent thermal and plasma-assisted atomic layer deposition (ALD) in situ. The band offsets of the heterointerface were then studied by consecutive removal of the layers by argon sputtering, followed by in situ X-ray photoelectron spectroscopy. The valence band maximum and conduction band minimum of Al2O3 are found to be 1.1 eV below and 2.3 eV above those of ZnO, resulting in a type-I staggered heterojunction. An apparent reduction of ZnO to elemental Zn in the interface region was detected in the Zn 2p core level and Zn L3MM Auger spectra. This suggests an interface formation different from previous models. The reduction of ZnO to Zn in the interface region accompanied by the creation of oxygen vacancies in ZnO results in an upward band bending at the interface. Therefore, this study suggests that interfacial properties such as the band bending as well as the valence and conduction band offsets should be in situ controllable to a certain extent by careful selection of the process parameters.
KW - ALD heterojunction
KW - band alignement
KW - ZnO
KW - Al2O3
KW - interface properties
Y1 - 2022
U6 - https://doi.org/10.1039/D1DT04008A
SN - 1477-9234
SN - 1477-9226
VL - 51
SP - 9291
EP - 9301
ER -
TY - GEN
A1 - Pérez, Eduardo
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Perez-Bosch Quesada, Emilio
A1 - Wenger, Christian
T1 - In-depth characterization of switching dynamics in amorphous HfO2 memristive arrays for the implementation of synaptic updating rules
T2 - Japanese Journal of Applied Physics
N2 - Accomplishing truly analog conductance modulation in memristive arrays is crucial in order to implement the synaptic plasticity in hardware-based neuromorphic systems. In this paper, such a feature was addressed by exploiting the inherent stochasticity of switching dynamics in amorphous HfO2 technology. A thorough statistical analysis of experimental characteristics measured in 4 kbit arrays by using trains of identical depression/potentiation pulses with different voltage amplitudes and pulse widths provided the key to develop two different updating rules and to define their optimal programming parameters. The first rule is based on applying a specific number of identical pulses until the conductance value achieves the
desired level. The second one utilized only one single pulse with a particular amplitude to achieve the targeted conductance level. In addition, all the results provided by the statistical analysis performed may play an important role in understanding better the switching behavior of this particular technology.
KW - RRAM
KW - memristive device
KW - HfO2
KW - memristive switching
Y1 - 2022
U6 - https://doi.org/10.35848/1347-4065/ac6a3b
SN - 0021-4922
VL - 61
SP - 1
EP - 7
ER -
TY - GEN
A1 - Baroni, Andrea
A1 - Glukhov, Artem
A1 - Pérez, Eduardo
A1 - Wenger, Christian
A1 - Calore, Enrico
A1 - Schifano, Sebastiano Fabio
A1 - Olivo, Piero
A1 - Ielmini, Daniele
A1 - Zambelli, Cristian
T1 - An energy-efficient in-memory computing architecture for survival data analysis based on resistive switching memories
T2 - Frontiers in Neuroscience
N2 - One of the objectives fostered in medical science is the so-called precision medicine, which requires the analysis of a large amount of survival data from patients to deeply understand treatment options. Tools like Machine Learning and Deep Neural Networks are becoming a de-facto standard. Nowadays, computing facilities based on the Von Neumann architecture are devoted to these tasks, yet rapidly hitting a bottleneck in performance and energy efficiency. The In-Memory Computing (IMC) architecture emerged as a revolutionary approach to overcome that issue. In this work, we propose an IMC architecture based on Resistive switching memory (RRAM) crossbar arrays to provide a convenient primitive for matrix–vector multiplication in a single computational step. This opens massive performance improvement in the acceleration of a neural network that is frequently used in survival analysis of biomedical records, namely the DeepSurv. We explored how the synaptic weights mapping strategy and the programming algorithms developed to counter RRAM non-idealities expose a performance/energy trade-off. Finally, we assessed the benefits of the proposed architectures with respect to a GPU-based realization of the same task, evidencing a tenfold improvement in terms of performance and three orders of magnitude with respect to energy efficiency.
KW - RRAM
KW - In-Memory Computing
KW - Multilevel switching
Y1 - 2022
U6 - https://doi.org/10.3389/fnins.2022.932270
SN - 1662-4548
VL - Vol. 16
SP - 1
EP - 16
ER -
TY - GEN
A1 - Bogun, Nicolas
A1 - Perez-Bosch Quesada, Emilio
A1 - Pérez, Eduardo
A1 - Wenger, Christian
A1 - Kloes, Alexander
A1 - Schwarz, Mike
T1 - Analytical Calculation of Inference in Memristor-based Stochastic Artificial Neural Networks
T2 - 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), 23-24 June 2022 , Wrocław, Poland
N2 - The impact of artificial intelligence on human life
has increased significantly in recent years. However, as the
complexity of problems rose aswell, increasing system features
for such amount of data computation became troublesome due
to the von Neumann’s computer architecture. Neuromorphic
computing aims to solve this problem by mimicking the parallel
computation of a human brain. For this approach, memristive
devices are used to emulate the synapses of a human brain. Yet,
common simulations of hardware based networks require time
consuming Monte-Carlo simulations to take into account the
stochastic switching of memristive devices. This work presents
an alternative concept making use of the convolution of the
probability distribution functions (PDF) of memristor currents
by its equivalent multiplication in Fourier domain. An artificial
neural network is accordingly implemented to perform the
inference stage with handwritten digits.
KW - RRAM
KW - neural network
Y1 - 2022
SN - 978-83-63578-22-0
SN - 978-83-63578-21-3
SN - 978-1-6654-6176-4
U6 - https://doi.org/10.23919/MIXDES55591.2022.9838321
SP - 83
EP - 88
ER -
TY - GEN
A1 - Lukosius, Mindaugas
A1 - Lukose, Rasuolė
A1 - Lisker, Marco
A1 - Luongo, G.
A1 - Elviretti, M.
A1 - Mai, Andreas
A1 - Wenger, Christian
T1 - Graphene Research in 200 mm CMOS Pilot Line
T2 - 45th Jubilee International Convention on Information, Communication and Electronic Technology (MIPRO), 2022
N2 - Due to the unique electronic structures, graphene and other 2D Materials are considered as materials which can enable and extend the functionalities and performance in a large variety of applications, among them in microelectronics. At this point, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance.Towards these goals, this paper focuses on the full spectra of graphene research aspects in 200mm pilot line. We investigated different process module developments such as CMOS compatible growth of high quality graphene on germanium and its growth mechanisms, transfer related challenges on target substrates, patterning, passivation and various concepts of contacting of graphene on a full 200 mm wafers. Finally, we fabricated proof-of-concept test structures e.g. TLM, Hall bars and capacitor structures to prove the feasibility of graphene processing in the pilot line of IHP.
KW - Graphene
KW - CMOS
Y1 - 2022
SN - 978-953-233-103-5
SN - 978-953-233-102-8
SN - 978-1-6654-8434-3
U6 - https://doi.org/10.23919/MIPRO55190.2022.9803362
SN - 2623-8764
SN - 1847-3938
SP - 113
EP - 117
ER -
TY - GEN
A1 - Strobel, Carsten
A1 - Alvarado Chavarin, Carlos
A1 - Richter, Karola
A1 - Knaut, Martin
A1 - Reif, Johanna
A1 - Völkel, Sandra
A1 - Jahn, Andreas
A1 - Albert, Matthias
A1 - Wenger, Christian
A1 - Kirchner, Robert
A1 - Bartha, Johann Wolfgang
A1 - Mikolajick, Thomas
T1 - Novel Graphene Adjustable-Barrier Transistor with Ultra-High Current Gain
T2 - ACS Applied Materials & Interfaces
N2 - A graphene-based three terminal barristor device was proposed to overcome the low on/off ratios and insufficient current saturation of conventional graphene field effect transistors. In this study, we fabricated and analyzed a novel graphene-based transistor, which resembles the structure of the barristor but uses a different operating condition. This new device, termed graphene adjustable-barriers transistor (GABT), utilizes a semiconductor-based gate rather than a metal−insulator gate structure to modulate the device currents. The key feature of the device is the two graphene-semiconductor Schottky barriers with different heights that are controlled simultaneously by the gate voltage. Due to the asymmetry of the barriers, the drain current exceeds the gate current by several orders of magnitude. Thus, the GABT can be considered an amplifier with an alterable current gain. In this work, a silicon−graphene−germanium GABT with an ultra-high current gain (ID/IG up to 8 × 106) was fabricated, and the device functionality was demonstrated. Additionally, a capacitance model is applied to predict the theoretical device performance resulting in an on−off ratio above 106, a swing of 87 mV/dec, and a drivecurrent of about 1 × 106 A/cm2.
KW - Graphene
KW - Transistor
Y1 - 2022
U6 - https://doi.org/10.1021/acsami.2c10634
SN - 1944-8244
SN - 1944-8252
VL - 14
IS - 34
SP - 39249
EP - 39254
ER -
TY - GEN
A1 - Baroni, Andrea
A1 - Glukhov, Artem
A1 - Pérez, Eduardo
A1 - Wenger, Christian
A1 - Ielmini, Daniele
A1 - Olivo, Piero
A1 - Zambelli, Cristian
T1 - Low Conductance State Drift Characterization and Mitigation in Resistive Switching Memories (RRAM) for Artificial Neural Networks
T2 - IEEE Transactions on Device and Materials Reliability
N2 - The crossbar structure of Resistive-switching random access memory (RRAM) arrays enabled the In-Memory Computing circuits paradigm, since they imply the native acceleration of a crucial operations in this scenario, namely the Matrix-Vector-Multiplication (MVM). However, RRAM arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation. A critical
one is related to the drift of the low conductance states appearing
immediately at the end of program and verify algorithms that
are mandatory for an accurate multi-level conductance operation. In this work, we analyze the benefits of a new programming
algorithm that embodies Set and Reset switching operations to
achieve better conductance control and lower variability. Data
retention analysis performed with different temperatures for 168
hours evidence its superior performance with respect to standard programming approach. Finally, we explored the benefits
of using our methodology at a higher abstraction level, through
the simulation of an Artificial Neural Network for image recognition task (MNIST dataset). The accuracy achieved shows higher
performance stability over temperature and time.
KW - RRAM
KW - neural network
KW - Multilevel switching
Y1 - 2022
U6 - https://doi.org/10.1109/TDMR.2022.3182133
SN - 1530-4388
VL - 22
IS - 3
SP - 340
EP - 347
ER -
TY - GEN
A1 - Prüfer, Mareike
A1 - Wenger, Christian
A1 - Bier, Frank F.
A1 - Laux, Eva-Maria
A1 - Hölzel, Ralph
T1 - Activity of AC electrokinetically immobilized horseradish peroxidase
T2 - Electrophoresis
N2 - Dielectrophoresis(DEP) is an AC electrokinetic effect mainly used to manipulate cells.Smaller particles,like virions,antibodies,enzymes,andevendyemolecules can be immobilized by DEP as well. In principle, it was shown that enzymesare active after immobilization by DEP, but no quantification of the retainedactivity was reported so far. In this study, the activity of the enzyme horseradishperoxidase (HRP) is quantified after immobilization by DEP. For this, HRP is immobilized on regular arrays of titanium nitride ring electrodes of 500 nm diameter and 20 nm widths. The activity of HRP on the electrode chip is measured with a limit of detection of 60 fg HRP by observing the enzymatic turnover of Amplex Red and H2O2 to fluorescent resoruf in by fluorescence microscopy. The initial activity of the permanently immobilized HRP equals up to 45% of the activity that can be expected for an ideal monolayer of HRP molecules on all electrodes of the array. Localization of the immobilizate on the electrodesis accomplished by staining with the fluorescent product of the enzyme reac-tion.The high residual activity of enzymes after AC field induced immobilization shows the method’s suitability for biosensing and research applications.
KW - dielectrophoresis
KW - immobilization
KW - nanoelectrodes
Y1 - 2022
U6 - https://doi.org/10.1002/elps.202200073
SN - 1522-2683
VL - 43
IS - 18-19
SP - 1920
EP - 1933
ER -
TY - GEN
A1 - Franck, Max
A1 - Dabrowski, Jaroslaw
A1 - Schubert, Markus Andreas
A1 - Wenger, Christian
A1 - Lukosius, Mindaugas
T1 - Towards the Growth of Hexagonal Boron Nitride on Ge(001)/Si Substrates by Chemical Vapor Deposition
T2 - Nanomaterials
N2 - The growth of hexagonal boron nitride (hBN) on epitaxial Ge(001)/Si substrates via high-vacuum chemical vapor deposition from borazine is investigated for the first time in a systematic manner. The influences of the process pressure and growth temperature in the range of 10−7–10−3 mbar and 900–980 °C, respectively, are evaluated with respect to morphology, growth rate, and crystalline quality of the hBN films. At 900 °C, nanocrystalline hBN films with a lateral crystallite size of ~2–3 nm are obtained and confirmed by high-resolution transmission electron microscopy images. X-ray photoelectron spectroscopy confirms an atomic N:B ratio of 1 ± 0.1. A three-dimensional growth mode is observed by atomic force microscopy. Increasing the process pressure in the reactor mainly affects the growth rate, with only slight effects on crystalline quality and none on the principle growth mode. Growth of hBN at 980 °C increases the average crystallite size and leads to the formation of 3–10 well-oriented, vertically stacked layers of hBN on the Ge surface. Exploratory ab initio density functional theory simulations indicate that hBN edges are saturated by hydrogen, and it is proposed that partial de-saturation by H radicals produced on hot parts of the set-up is responsible for the growth
KW - Boron nitride
KW - 2d materials
KW - Chemical vapour deposition
Y1 - 2022
U6 - https://doi.org/10.3390/nano12193260
SN - 2079-4991
VL - 12
IS - 19
ER -
TY - GEN
A1 - Glukhov, Artem
A1 - Lepri, Nicola
A1 - Milo, Valerio
A1 - Baroni, Andrea
A1 - Zambelli, Cristian
A1 - Olivo, Piero
A1 - Pérez, Eduardo
A1 - Wenger, Christian
A1 - Ielmini, Daniele
T1 - End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays
T2 - Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022)
N2 - Resistive-switching random access memory (RRAM) is a promising technology that enables advanced applications in the field of in-memory computing (IMC). By operating the memory array in the analogue domain, RRAM-based IMC architectures can dramatically improve the energy efficiency of deep neural networks (DNNs). However, achieving a high inference accuracy is challenged by significant variation of RRAM conductance levels, which can be compensated by (i) advanced programming techniques and (ii) variability-aware training (VAT) algorithms. In both cases, however, detailed knowledge and accurate physics-based statistical models of RRAM are needed to develop programming and VAT methodologies. This work presents an end-to-end approach to the development of highly-accurate IMC circuits with RRAM, encompassing the device modeling, the precise programming algorithm, and the VAT simulations to maximize the DNN classification accuracy in presence of conductance variations.
KW - RRAM
KW - HfO2
KW - neural network
KW - memristive switching
Y1 - 2022
U6 - https://doi.org/10.1109/VLSI-SoC54400.2022.9939653
SP - 1
EP - 5
ER -
TY - GEN
A1 - Wen, Jianan
A1 - Baroni, Andrea
A1 - Pérez, Eduardo
A1 - Ulbricht, Markus
A1 - Wenger, Christian
A1 - Krstic, Milos
T1 - Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages
T2 - 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
N2 - RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states.
KW - RRAM
KW - Multilevel switching
KW - AI accelarator
Y1 - 2022
SN - 978-1-6654-5938-9
SN - 978-1-6654-5937-2
U6 - https://doi.org/10.1109/DFT56152.2022.9962345
SN - 2765-933X
SP - 1
EP - 6
ER -
TY - GEN
A1 - Pérez, Eduardo
A1 - Maldonado, David
A1 - Perez-Bosch Quesada, Emilio
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Jimenez-Molinos, Francisco
A1 - Wenger, Christian
T1 - Parameter Extraction Methods for Assessing Device-to-Device and Cycle-to-Cycle Variability of Memristive Devices at Wafer Scale
T2 - IEEE Transactions on Electron Devices
N2 - The stochastic nature of the resistive switching (RS) process in memristive devices makes device-to-device (DTD) and cycle-to-cycle (CTC) variabilities relevant magnitudes to be quantified and modeled. To accomplish this aim, robust and reliable parameter extraction methods must be employed. In this work, four different extraction methods were used at the production level (over all the 108 devices integrated on 200-mm wafers manufactured in the IHP 130-nm CMOS technology) in order to obtain the corresponding collection of forming, reset, and set switching voltages. The statistical analysis of the experimental data (mean and standard deviation (SD) values) was plotted by using heat maps, which provide a good summary of the whole data at a glance and, in addition, an easy manner to detect inhomogeneities in the fabrication process.
KW - RRAM
KW - memristive device
KW - cycle-to-cycle variability
KW - device-to-device variability
Y1 - 2023
U6 - https://doi.org/10.1109/TED.2022.3224886
SN - 0018-9383
VL - 70
IS - 1
SP - 360
EP - 365
ER -
TY - GEN
A1 - Nitsch, Paul-G.
A1 - Ratzke, Markus
A1 - Pozarowska, Emilia
A1 - Flege, Jan Ingo
A1 - Alvarado Chavarin, Carlos
A1 - Wenger, Christian
A1 - Fischer, Inga Anita
T1 - Deposition of reduced ceria thin films by reactive magnetron sputtering for the development of a resistive gas sensor
T2 - Verhandlungen der DPG, Berlin 2024
N2 - The use of cerium oxide for hydrogen sensing is limited by the low electrical conductivity of layers deposited from a ceria target. To increase the electrical conductivity, partially reduced cerium oxide layers were obtained from a metallic cerium target by reactive magnetron sputtering. The proportions of the oxidation states Ce3+, present in reduced species, and Ce4+, present in fully oxidized species, were determined by ex-situ XPS. For electrical characterization, films were deposited on planarized tungsten finger electrodes. IV curves were measured over several days to investigate possible influences of oxygen and humidity on electrical conductivity. The morphological stability of the layers under ambient conditions was investigated by microscopical methods. The XPS results show a significant amount of Ce3+ in the layers. The electrical conductivity of as-grown samples is several orders of magnitude higher than that of samples grown from a ceria target. However, the conductivity decreases over time, indicating an oxidation of the layers. The surface morphology of the samples was found to be changing drastically within days, leading to partial delamination.
KW - ceria
KW - metalic cerium target
KW - electrical conductivity
KW - X-ray photoelectron spectroscopy (XPS)
KW - oxidation states
KW - morphology
Y1 - 2024
UR - https://www.dpg-verhandlungen.de/year/2024/conference/berlin/part/ds/session/11/contribution/18
SN - 0420-0195
PB - Deutsche Physikalische Gesellschaft
CY - Bad Honnef
ER -
TY - GEN
A1 - Strobel, Carsten
A1 - Alvarado Chavarin, Carlos
A1 - Knaut, Martin
A1 - Völkel, Sandra
A1 - Albert, Matthias
A1 - Hiess, Andre
A1 - Max, Benjamin
A1 - Wenger, Christian
A1 - Kirchner, Robert
A1 - Mikolajick, Thomas
T1 - High Gain Graphene Based Hot Electron Transistor with Record High Saturated Output Current Density
T2 - Advanced Electronic Materials
N2 - Hot electron transistors (HETs) represent an exciting frontier in semiconductor technology, holding the promise of high-speed and high-frequency electronics. With the exploration of two-dimensional materials such as graphene and new device architectures, HETs are poised to revolutionize the landscape of modern electronics. This study highlights a novel HET structure with a record output current density of 800 A/cm² and a high current gain α, fabricated using a scalable fabrication approach. The HET structure comprises two-dimensional hexagonal boron nitride (hBN) and graphene layers wet transferred to a germanium substrate. The combination of these materials results in exceptional performance, particularly in terms of the highly saturated output current density. The scalable fabrication scheme used to produce the HET opens up opportunities for large-scale manufacturing. This breakthrough in HET technology holds promise for advanced electronic applications, offering high current capabilities in a practical and manufacturable device.
KW - Graphene
KW - Transistor
Y1 - 2024
U6 - https://doi.org/10.1002/aelm.202300624
SN - 2199-160X
VL - 10
IS - 2
ER -
TY - GEN
A1 - Pechmann, Stefan
A1 - Pérez, Eduardo
A1 - Wenger, Christian
A1 - Hagelauer, Amelie
T1 - A current mirror Based read circuit design with multi-level capability for resistive switching deviceb
T2 - 2024 International Conference on Electronics, Information, and Communication (ICEIC)
N2 - This paper presents a read circuit design for resistive memory cells based on current mirrors. The circuit utilizes high-precision current mirrors and reference cells to determine the state of resistive memory using comparators. It offers a high degree in adaptability in terms of both resistance range and number of levels. Special emphasis was put on device protection to prevent accidental programming of the memory during read operations. The realized circuit can resolve eight states with a resolution of up to 1 k Ω, realizing a digitization of the analog memory information. Furthermore, the integration in a complete memory macro is shown. The circuit was realized in a 130 nm-process but can easily be adapted to other processes and resistive memory technologies.
KW - RRAM
KW - memristive device
Y1 - 2024
SN - 979-8-3503-7188-8
U6 - https://doi.org/10.1109/ICEIC61013.2024.10457188
SN - 2767-7699
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
TY - GEN
A1 - Nikiruy, Kristina
A1 - Pérez, Eduardo
A1 - Baroni, Andrea
A1 - Dorai Swamy Reddy, Keerthi
A1 - Pechmann, Stefan
A1 - Wenger, Christian
A1 - Ziegler, Martin
T1 - Blooming and pruning: learning from mistakes with memristive synapses
T2 - Scientific Reports
N2 - AbstractBlooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. This approach provides hardware, local, and energy-efficient learning. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks.
KW - RRAM
KW - Neural network
Y1 - 2024
U6 - https://doi.org/10.1038/s41598-024-57660-4
SN - 2045-2322
VL - 14
IS - 1
ER -
TY - CHAP
A1 - Wen, Jianan
A1 - Vargas, Fabian Luis
A1 - Zhu, Fukun
A1 - Reiser, Daniel
A1 - Baroni, Andrea
A1 - Fritscher, Markus
A1 - Pérez, Eduardo
A1 - Reichenbach, Marc
A1 - Wenger, Christian
A1 - Krstic, Milos
T1 - Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment
T2 - 2024 IEEE 25th Latin American Test Symposium (LATS)
N2 - Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation.
KW - RRAM
Y1 - 2024
U6 - https://doi.org/10.1109/LATS62223.2024.10534601
PB - IEEE
ER -
TY - GEN
A1 - Dorai Swamy Reddy, Keerthi
A1 - Pérez, Eduardo
A1 - Baroni, Andrea
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Marschmeyer, Steffen
A1 - Fraschke, Mirko
A1 - Lisker, Marco
A1 - Wenger, Christian
A1 - Mai, Andreas
T1 - Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance
T2 - The European Physical Journal B
N2 - Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.
KW - RRAM
Y1 - 2024
U6 - https://doi.org/10.1140/epjb/s10051-024-00821-1
SN - 1434-6028
VL - 97
PB - Springer Science and Business Media LLC
ER -
TY - GEN
A1 - Jia, Ruolan
A1 - Pechmann, Stefan
A1 - Markus, Fritscher
A1 - Wenger, Christian
A1 - Zhang, Lei
A1 - Hagelauer, Amelie
T1 - Soft-Error Analysis of RRAM 1T1R Compute-In-Memory Core for Artificial Neural Networks
T2 - 2024 39th Conference on Design of Circuits and Integrated Systems (DCIS)
N2 - This work analyses SEU-induced soft-errors in analog compute-in-memory cores using resistive random-access memory (RRAM) for artificial neural networks, where their bitcells utilize one-transistor-one-RRAM (1T1R) structure. This is modeled by combining the Stanford-PKU RRAM Model and the model of the radiation-induced photocurrent in access transistors. As results, this work derives the maximal RRAM crossbar size without occurring any logic flip and indicates the requirements for RRAM technology to achieve a SEU-resilient 1T1R compute-in memory cores.
KW - RRAM
Y1 - 2024
U6 - https://doi.org/10.1109/DCIS62603.2024.10769203
SP - 1
EP - 5
PB - IEEE
ER -
TY - GEN
A1 - Perez-Bosch Quesada, Emilio
A1 - Mistroni, Alberto
A1 - Jia, Ruolan
A1 - Dorai Swamy Reddy, Keerthi
A1 - Reichmann, Felix
A1 - Castan, Helena
A1 - Dueñas, Salvador
A1 - Wenger, Christian
A1 - Perez, Eduardo
T1 - Forming and resistive switching of HfO₂-based RRAM devices at cryogenic temperature
T2 - IEEE Electron Device Letters
N2 - Reliable data storage technologies able to operate at cryogenic temperatures are critical to implement scalable quantum computers and develop deep-space exploration systems, among other applications. Their scarce availability is pushing towards the development of emerging memories that can perform such storage in a non-volatile fashion. Resistive Random-Access Memories (RRAM) have demonstrated their switching capabilities down to 4K. However, their operability at lower temperatures still remain as a challenge. In this work, we demonstrate for the first time the forming and resistive switching capabilities of CMOS-compatible RRAM devices at 1.4K. The HfO2-based devices are deployed following an array of 1-transistor-1-resistor (1T1R) cells. Their switching performance at 1.4K was also tested in the multilevel-cell (MLC) approach, storing up to 4 resistance levels per cell.
KW - RRAM
Y1 - 2024
U6 - https://doi.org/10.1109/LED.2024.3485873
SN - 0741-3106
VL - 45
IS - 12
SP - 2391
EP - 2394
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
TY - GEN
A1 - Weißhaupt, David
A1 - Sürgers, Christoph
A1 - Bloos, Dominik
A1 - Funk, Hannes Simon
A1 - Oehme, Michael
A1 - Fischer, Gerda
A1 - Schubert, Markus Andreas
A1 - Wenger, Christian
A1 - van Slageren, Joris
A1 - Fischer, Inga Anita
A1 - Schulze, Jörg
T1 - Lateral Mn5Ge3 spin-valve in contact with a high-mobility Ge two-dimensional hole gas
T2 - Semiconductor Science and Technology
N2 - Abstract
Ge two-dimensional hole gases (2DHG) in strained modulation-doped quantum-wells represent a promising material platform for future spintronic applications due to their excellent spin transport properties and the theoretical possibility of efficient spin manipulation. Due to the continuous development of epitaxial growth recipes extreme high hole mobilities and low effective masses can be achieved, promising an efficient spin transport. Furthermore, the Ge 2DHG can be integrated in the well-established industrial complementary metal-oxide-semiconductor (CMOS) devices technology. However, efficient electrical spin injection into a Ge 2DHG—an essential prerequisite for the realization of spintronic devices—has not yet been demonstrated. In this work, we report the fabrication and low-temperature magnetoresistance (MR) measurements of a laterally structured Mn5Ge3/Ge 2DHG/ Mn5Ge3 device. The ferromagnetic Mn5Ge3 contacts are grown directly into the Ge quantum well by means of an interdiffusion process with a spacing of approximately 130 nm, forming a direct electrical contact between the ferromagnetic metal and the Ge 2DHG. Here, we report for the first time a clear MR signal for temperatures below 13 K possibly arising from successful spin injection into the high mobility Ge 2DHG. The results represent a step forward toward the realization of CMOS compatible spintronic devices based on a 2DHG.
KW - two-dimensional hole gas
Y1 - 2024
U6 - https://doi.org/10.1088/1361-6641/ad8d06
SN - 0268-1242
VL - 39
IS - 12
SP - 1
EP - 10
PB - IOP Publishing
ER -
TY - GEN
A1 - Capista, Daniele
A1 - Lukose, Rasuole
A1 - Majnoon, Farnaz
A1 - Lisker, Marco
A1 - Wenger, Christian
A1 - Lukosius, Mindaugas
T1 - Optimization of the metal deposition process for the accurate estimation of Low Metal-Graphene Contact-Resistance
T2 - 47th MIPRO ICT and Electronics Convention (MIPRO), 20-24 May 2024, Opatija, Croatia
Y1 - 2024
SN - 979-8-3503-8250-1
SN - 979-8-3503-8249-5
U6 - https://doi.org/10.1109/MIPRO60963.2024.10569895
SN - 2623-8764
ER -
TY - GEN
A1 - Maldonado, David
A1 - Cantudo, Antonio
A1 - Swamy Reddy, Keerthi Dorai
A1 - Pechmann, Stefan
A1 - Uhlmann, Max
A1 - Wenger, Christian
A1 - Roldan, Juan Bautista
A1 - Pérez, Eduardo
T1 - Influence of stop and gate voltage on resistive switching of 1T1R HfO2-based memristors, a modeling and variability analysis
T2 - Materials Science in Semiconductor Processing
Y1 - 2024
U6 - https://doi.org/10.1016/j.mssp.2024.108726
SN - 1873-4081
SN - 1369-8001
VL - 182
ER -
TY - GEN
A1 - Kosto, Yuliia
A1 - Tschammer, Rudi
A1 - Morales, Carlos
A1 - Henkel, Karsten
A1 - Flege, Jan Ingo
A1 - Ratzke, Markus
A1 - Fischer, Inga Anita
A1 - Costina, Ioan
A1 - Alvarado Chavarin, Carlos
A1 - Wenger, Christian
T1 - Rational design and development of room temperature hydrogen sensors compatible with CMOS technology: a necessary step for the coming renewable hydrogen economy
T2 - Proceedings of iCampus Conference Cottbus 2024
N2 - The transition towards a new, renewable energy system based on green energy vectors, such as hydrogen, requires not only direct energy conversion and storage systems, but also the development of auxiliary components, such as highly sensitive hydrogen gas sensors integrated into mass devices that operate at ambient conditions. Despite the recent advances in nanostructured metal oxide thin films in terms of simple fabrication processes and compatibility with integrated circuits, high sensitivity, and short response/recovery times usually require the use of expensive noble metals or elevated tem-peratures (>250 ºC), which results in high power consumption and poor long-term stability. This article presents the first steps of the work on developing a novel resistive hydrogen gas sensor based on ultrathin cerium oxide films, compatible with complementary metal oxide semiconductor technology and capable of operating at room temperature. Here, we show a multidisciplinary bottom-up approach combining different work areas for the sensor development, such as sensor architecture, sensing mechanism and deposition strategy of the active layer, electrical contact design depending on the desired electrical output, and fast testing under controlled environments.
KW - gas sensors
KW - micro-structering
KW - atomic layer deposition
KW - sensor platform
Y1 - 2024
SN - 978-3-910600-00-3
U6 - https://doi.org/10.5162/iCCC2024/P21
SP - 182
EP - 185
PB - AMA Service GmbH
CY - Wunstorf
ER -
TY - GEN
A1 - Vinuesa, Guillermo
A1 - García, Héctor
A1 - Pérez, Eduardo
A1 - Wenger, Christian
A1 - Íñiguez de la Torre, Ignacio
A1 - González, Tomás
A1 - Dueñas, Salvador
A1 - Castán, Helena
T1 - On the asymmetry of Resistive Switching Transitions
T2 - Electronics
N2 - In this study, the resistive switching phenomena in TiN/Ti/HfO2/Ti metal–insulator–metal stacks is investigated, mainly focusing on the analysis of set and reset transitions. The electrical measurements in a wide temperature range reveal that the switching transitions require less voltage (and thus, less energy) as temperature rises, with the reset process being much more temperature sensitive. The main conduction mechanism in both resistance states is Space-charge-limited Conduction, but the high conductivity state also shows Schottky emission, explaining its temperature dependence. Moreover, the temporal evolution of these transitions reveals clear differences between them, as their current transient response is completely different. While the set is sudden, the reset process development is clearly non-linear, closely resembling a sigmoid function. This asymmetry between switching processes is of extreme importance in the manipulation and control of the multi-level characteristics and has clear implications in the possible applications of resistive switching devices in neuromorphic computing.
KW - resistive switching
KW - RRAM
KW - memristor
KW - transient
KW - temperature dependence
KW - low power consumption
Y1 - 2024
U6 - https://doi.org/10.3390/electronics13132639
SN - 2079-9292
VL - 13
IS - 13
PB - MDPI
ER -
TY - GEN
A1 - Strobel, Carsten
A1 - Alvarado Chavarin, Carlos
A1 - Knaut, Martin
A1 - Albert, Matthias
A1 - Heinzig, André
A1 - Gummadi, Likhith
A1 - Wenger, Christian
A1 - Mikolajick, Thomas
ED - Giannazzo, Filippo
ED - Agnello, Simonpietro
ED - Seravalli, Luca
ED - Bondino, Federica
T1 - p-Type Schottky contacts for graphene adjustable-Barrier phototransistors
T2 - Nanomaterials
N2 - The graphene adjustable-barriers phototransistor is an attractive novel device for potential high speed and high responsivity dual-band photodetection. In this device, graphene is embedded between the semiconductors silicon and germanium. Both n-type and p-type Schottky contacts between graphene and the semiconductors are required for this device. While n-type Schottky contacts are widely investigated, reports about p-type Schottky contacts between graphene and the two involved semiconductors are scarce. In this study, we demonstrate a p-type Schottky contact between graphene and p-germanium. A clear rectification with on–off ratios of close to 10 3 (±5 V) and a distinct photoresponse at telecommunication wavelengths in the infrared are achieved. Further, p-type silicon is transferred to or deposited on graphene, and we also observe rectification and photoresponse in the visible range for some of these p-type Schottky junctions. These results are an important step toward the realization of functional graphene adjustable-barrier phototransistors.
KW - phototransistor
KW - GABT
KW - graphene
KW - p-type
KW - silicon
KW - germanium
KW - high responsivity
KW - high speed
KW - dual-band
KW - photodetection
Y1 - 2024
U6 - https://doi.org/10.3390/nano14131140
SN - 2079-4991
VL - 14
IS - 13
PB - MDPI
ER -
TY - GEN
A1 - Morales, Carlos
A1 - Plate, Paul
A1 - Marth, Ludwig
A1 - Naumann, Franziska
A1 - Kot, Małgorzata
A1 - Janowitz, Christoph
A1 - Kus, Peter
A1 - Zöllner, Marvin Hartwig
A1 - Wenger, Christian
A1 - Henkel, Karsten
A1 - Flege, Jan Ingo
T1 - Bottom-up design of a supercycle recipe for atomic layer deposition of tunable Indium Gallium Zinc Oxide thin films
T2 - ACS Applied Electronic Materials
N2 - We present a successful bottom-up approach to design a generic plasma-enhanced atomic layer deposition (PEALD) supercycle recipe to grow high-quality indium gallium zinc oxide (IGZO) thin films with tunable composition at a relatively low temperature of 150 °C. In situ real-time ellipsometric characterization in combination with ex situ complementary techniques has been used to optimize the deposition process and quality of the films by identifying and solving growth challenges such as degree of oxidation, nucleation delays, or elemental composition. The developed supercycle approach enables facile control of the target composition by adapting the subcycle ratios within the supercycle process. Compared to other low-temperature deposition techniques resulting in amorphous films, our PEALD–IGZO process at 150 °C results in nearly amorphous, nanocrystalline films. The preparation of IGZO films at low temperature by a supercycle PEALD approach allows controlling the thickness, composition, and electrical properties while preventing thermally induced segregation.
KW - IGZO
KW - PEALD
KW - supercycle
KW - XPS depth profiling
KW - current density
Y1 - 2024
U6 - https://doi.org/10.1021/acsaelm.4c00730
SN - 2637-6113
VL - 6
IS - 8
SP - 5694
EP - 5704
PB - American Chemical Society (ACS)
ER -
TY - GEN
A1 - Hayat, Ahsan
A1 - Ratzke, Markus
A1 - Alvarado Chavarin, Carlos
A1 - Zöllner, Marvin Hartwig
A1 - Corley-Wiciak, Agnieszka Anna
A1 - Schubert, Markus Andreas
A1 - Wenger, Christian
A1 - Fischer, Inga Anita
T1 - Structural and morphological properties of CeO2 films deposited by radio frequency magnetron sputtering for back-end-of-line integration
T2 - Thin Solid Films
Y1 - 2024
U6 - https://doi.org/10.1016/j.tsf.2024.140547
SN - 0040-6090
VL - 807
ER -
TY - GEN
A1 - Fritscher, Markus
A1 - Singh, Simranjeet
A1 - Rizzi, Tommaso
A1 - Baroni, Andrea
A1 - Reiser, Daniel
A1 - Mallah, Maen
A1 - Hartmann, David
A1 - Bende, Ankit
A1 - Kempen, Tim
A1 - Uhlmann, Max
A1 - Kahmen, Gerhard
A1 - Fey, Dietmar
A1 - Rana, Vikas
A1 - Menzel, Stephan
A1 - Reichenbach, Marc
A1 - Krstic, Milos
A1 - Merchant, Farhad
A1 - Wenger, Christian
T1 - A flexible and fast digital twin for RRAM systems applied for training resilient neural networks
T2 - Scientific Reports
N2 - Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).
KW - RRAM
KW - Neural network
KW - digital twin
Y1 - 2024
U6 - https://doi.org/10.1038/s41598-024-73439-z
SN - 2045-2322
VL - 14
IS - 1
PB - Springer Science and Business Media LLC
ER -
TY - GEN
A1 - Lukosius, Mindaugas
A1 - Lukose, Rasuolė
A1 - Dubey, P. K.
A1 - Raju, A. I.
A1 - Capista, Daniele
A1 - Lisker, Marco
A1 - Mai, A.
A1 - Wenger, Christian
T1 - Graphene for photonic applications
T2 - 2024 47th MIPRO ICT and Electronics Convention (MIPRO)
N2 - Integrating graphene into Silicon Complementary Metal-Oxide-Semiconductor (CMOS) technology for photonic applications holds immense promise, but it encounters challenges in establishing large-scale graphene processes. These challenges encompass growth through techniques like Chemical Vapor Deposition (CVD), transfer, encapsulation, and contact formation within a routine 200mm wafer pilot line typically utilized for integrated circuit fabrication. This study is dedicated to exploring various facets of graphene research within a 200 mm pilot line, with a focus on overcoming challenges through the fabrication of proof-of-concept photonic graphene-based devices. The synthesis of graphene targeted epi-Ge(100)/Si(100) substrates, grown within the IHP pilot line, showcasing the potential for high-quality graphene deposition across 200mm wafers. Alternatively, employing different orientations such as (110) has been explored to enhance graphene mobility, achieving a remarkable mobility of 2300 cm 2 /Vs at present. The study systematically investigates graphene quality, thickness, and homogeneity utilizing techniques such as Raman spectroscopy, Atomic Force Microscopy (AFM), and Scanning Electron Microscopy (SEM). Additionally, simulations and fabrication of the graphene ring modulators have been conducted at both the component and device levels, incorporating realistic graphene properties. These results indicate a modulation depth of 1.6 dB/μm and a 3dB bandwidth of 7 GHz, showcasing the potential of graphene-based photonic devices for high-speed communication applications.
KW - Graphene
Y1 - 2024
SN - 979-8-3503-8250-1
SN - 979-8-3503-8249-5
U6 - https://doi.org/10.1109/MIPRO60963.2024.10569652
SN - 2623-8764
SP - 1614
EP - 1618
PB - IEEE
ER -
TY - GEN
A1 - Fritscher, Markus
A1 - Wenger, Christian
A1 - Krstic, Milos
T1 - From device to application - integrating RRAM Accelerator Blocks into large AI systems
T2 - 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
N2 - This work provides an introduction to design methodologies for RRAM-based systems. We illustrate the impact of device variation on the performance of neural networks and propose a circuit-level integration approach for RRAM-based compute blocks. Moreover, we demonstrate a possible architectural integration by incorporating RRAM-based VMM blocks fabricated in a 130 nm CMOS process into a RISC-V.
KW - RRAM
Y1 - 2024
SN - 979-8-3503-5411-9
SN - 979-8-3503-5412-6
U6 - https://doi.org/10.1109/ISVLSI61997.2024.00111
SN - 2159-3477
SP - 592
EP - 592
PB - IEEE
ER -
TY - GEN
A1 - Fritscher, Markus
A1 - Uhlmann, Max
A1 - Ostrovskyy, Philip
A1 - Reiser, Daniel
A1 - Chen, Junchao
A1 - Schubert, Andreas
A1 - Schulze, Carsten
A1 - Kahmen, Gerhard
A1 - Fey, Dietmar
A1 - Reichenbach, Marc
A1 - Krstic, Milos
A1 - Wenger, Christian
T1 - Area-efficient digital design using RRAM-CMOS standard cells
T2 - 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
N2 - Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 % smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 %. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core.
KW - RRAM
Y1 - 2024
SN - 979-8-3503-5411-9
SN - 979-8-3503-5412-6
U6 - https://doi.org/10.1109/ISVLSI61997.2024.00026
SN - 2159-3477
VL - 18
SP - 81
EP - 87
PB - IEEE
ER -
TY - GEN
A1 - Vinuesa, Guillermo
A1 - Garcia, Hector
A1 - Duenas, Salvador
A1 - Castan, Helena
A1 - Iñiguez de la Torre, Ignacio
A1 - Gonzalez, Tomas
A1 - Dorai Swamy Reddy, Keerthi
A1 - Uhlmann, Max
A1 - Wenger, Christian
A1 - Perez, Eduardo
T1 - Effect of the temperature on the performance and dynamic behavior of HfO2-Based Rram Devices
T2 - ECS Meeting Abstracts
N2 - Over the past decades, the demand for semiconductor memory devices has been steadily increasing, and is currently experiencing an unprecedented boost due to the development and expansion of artificial intelligence. Among emerging high-density non-volatile memories, resistive random-access memory (RRAM) is one of the best recourses for all kind of applications, such as neuromorphic computing or hardware security [1]. Although many materials have been evaluated for RRAM development, some of them with excellent results, HfO2 is one of the established materials in CMOS domain due to its compatibility with standard materials and processes [2].
The main goal of this work is to study the switching capability and stability of HfO2-based RRAMs, as well as to explore their ability in the field of analogue applications, by analyzing the evolution of the resistance states that allow multilevel control. Indeed, analogue operation is a key point for achieving electronic neural synapses in neuromorphic systems, with synaptic weight information encoded in the different resistance states. This research has been carried out over a wide temperature range, between 40 and 340 K, as we are interested in testing the extent to which performance is maintained or modified, with a view to designing neuromorphic circuits that are also suitable in the low-temperature realm. We aim to prove that these simple, fast, high integration density structures can also be used in circuits designed for specific applications, such as aerospace systems.
The RRAM devices studied in this work are TiN/Ti/8 nm-HfO2/TiN metal-insulator-metal (MIM) capacitors. Dielectric layers were atomic layer deposited (ALD). It has been demonstrated that the Ti coat in the top electrode acts as a scavenger that absorbs oxygen atoms from the HfO2 layer, and facilitates the creation of conductive filaments of oxygen vacancies [3]. In fact, the oxygen reservoir capability of Ti is well known, as it is able to attract and release oxygen atoms from or to the HfO2 layer during the RRAM operation [4]. The clustering of vacancies extends through the entire thickness of the oxide and, after an electroformig step, it joins the upper and lower electrodes and the device reaches the low resistance state (LRS). By applying adequate electrical signals, the filaments can be partially dissolved, which brings the device into the high-resistance state (HRS), with lower current values. The set process brings the device to the LRS state, while the reset one brings it to the HRS. The dependence of electrical conductivity on external applied electrical excitation allows triggering the device between the both states in a non-volatile manner [5].
The experimental equipment used consisted of a Keithley 4200-SCS semiconductor parameter analyzer and a Lake Shore cryogenic probe station. Fig.1 shows current-voltage cycles measured at different temperatures; the averages values at each temperature, both in logarithmic and linear scale, are also shown. The functional window increases as temperature decreases.
The evolutions of set and reset voltage values with temperature are depicted in Fig.2, whereas the current values (measured at 0.1 V) corresponding to the LRS and HRS can be seen in Fig.3. LRS resistance decreases as temperature increases, in agreement with semiconductor behaviour, probably due to a hopping conduction mechanism. Both set and reset voltages decrease as temperature increases; the reset process is smoother at high temperatures. The reduction in reset voltage variability as temperature increases is very notable.
Finally, Fig. 4 shows a picture of the transient behaviour; in the right panel of the same figure, the amplitudes of the current transients in the reset state have been included in the external loop.
To sum up, the resistive switching phenomena is studied in a wide temperature range. The LRS shows semiconducting behavior with temperature, most likely related to a hopping conduction mechanism. Switching voltages decrease as temperature increases, with a notable reduction in reset voltage variability. An excellent control of intermediate resistance state is shown through current transients at several voltages in the reset process.
REFERENCES
[1] M. Asif et al., Materials Today Electronics 1, 100004 (2022).
[2] S. Slesazeck et al., Nanotechnology 30, 352003 (2019).
[3] Z. Fang et al., IEEE Electron Device Letters 35, 9, 912-914 (2014).
[4] H. Y. Lee et al., IEEE Electron Device Letters 31, 1, 44-46 (2010).
[5] D. J. Wouters et al., Proceedings of the IEEE 103, 8, 1274-1288 (2015).
Figure 1
KW - RRAM
Y1 - 2024
U6 - https://doi.org/10.1149/MA2024-01211297mtgabs
SN - 2151-2043
VL - MA2024-01
IS - 21
SP - 1297
EP - 1297
PB - The Electrochemical Society
ER -
TY - GEN
A1 - Wen, Jianan
A1 - Baroni, Andrea
A1 - Perez, Eduardo
A1 - Uhlmann, Max
A1 - Fritscher, Markus
A1 - KrishneGowda, Karthik
A1 - Ulbricht, Markus
A1 - Wenger, Christian
A1 - Krstic, Milos
T1 - Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator
T2 - 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)
N2 - The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 % and 18 %, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero.
KW - RRAM
Y1 - 2024
SN - 978-3-9819263-8-5
SN - 979-8-3503-4860-6
U6 - https://doi.org/10.23919/DATE58400.2024.10546709
SN - 1558-1101
SP - 1
EP - 6
PB - IEEE
ER -
TY - GEN
A1 - Maldonado, David
A1 - Baroni, Andrea
A1 - Aldana, Samuel
A1 - Dorai Swamy Reddy, Keerthi
A1 - Pechmann, Stefan
A1 - Wenger, Christian
A1 - Roldán, Juan Bautista
A1 - Pérez, Eduardo
T1 - Kinetic Monte Carlo simulation analysis of the conductance drift in Multilevel HfO2-based RRAM devices
T2 - Nanoscale
N2 - The drift characteristics of valence change memory (VCM) devices have been analyzed through both experimental analysis and 3D kinetic Monte Carlo (kMC) simulations.
KW - RRAM
Y1 - 2024
U6 - https://doi.org/10.1039/d4nr02975e
SN - 2040-3364
VL - 16
IS - 40
SP - 19021
EP - 19033
PB - Royal Society of Chemistry (RSC)
ER -
TY - GEN
A1 - Uhlmann, Max
A1 - Rizzi, Tommaso
A1 - Wen, Jianan
A1 - Pérez-Bosch Quesada, Emilio
A1 - Al Beattie, Bakr
A1 - Ochs, Karlheinz
A1 - Pérez, Eduardo
A1 - Ostrovskyy, Philip
A1 - Carta, Corrado
A1 - Wenger, Christian
A1 - Kahmen, Gerhard
T1 - LUT-based RRAM model for neural accelerator circuit simulation
T2 - Proceedings of the 18th ACM International Symposium on Nanoscale Architectures
N2 - Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices’ models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP’s 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis.
KW - RRAM
KW - Neural network
Y1 - 2023
U6 - https://doi.org/10.1145/3611315.3633273
SP - 1
EP - 6
PB - ACM
CY - New York, NY, USA
ER -
TY - GEN
A1 - Strobel, Carsten
A1 - Alvarado Chavarin, Carlos
A1 - Völkel, Sandra
A1 - Jahn, Andreas
A1 - Hiess, Andre
A1 - Knaut, Martin
A1 - Albert, Matthias
A1 - Wenger, Christian
A1 - Steinke, Olaff
A1 - Stephan, Ulf
A1 - Röhlecke, Sören
A1 - Mikolajick, Thomas
T1 - Enhanced Electrical Properties of Optimized Vertical Graphene-Base Hot Electron Transistors
T2 - ACS Applied Electronic Materials
N2 - The arrival of high-mobility two-dimensional materials like graphene leads to the renaissance of former vertical semiconductor–metal–semiconductor (SMS) hot electron transistors. Because of the monolayer thickness of graphene, improved SMS transistors with a semimetallic graphene-base electrode are now feasible for high-frequency applications. In this study we report about a device that consists of amorphous silicon, graphene, and crystalline silicon. For the first time, this device is fabricated by a four-mask lithography process which leads to significant improvements in the device performance. A strongly increased common-emitter current gain of 2% could be achieved while the on–off ratio improved to 1.6 × 105, which is already higher than predicted theoretically. This could be mainly attributed to better interface characteristics and decreased lateral dimensions of the devices. A cutoff frequency of approximately 26 MHz could be forecasted based on the DC measurements of the device.
KW - Graphene
KW - Transistor
Y1 - 2023
U6 - https://doi.org/10.1021/acsaelm.2c01725
SN - 2637-6113
VL - 5
IS - 3
SP - 1670
EP - 1675
ER -
TY - GEN
A1 - Kloes, Alexander
A1 - Bischoff, Carl
A1 - Leise, Jakob
A1 - Perez-Bosch Quesada, Emilio
A1 - Wenger, Christian
A1 - Pérez, Eduardo
T1 - Stochastic switching of memristors and consideration in circuit simulation
T2 - Solid State Electronics
N2 - We explore the stochastic switching of oxide-based memristive devices by using the Stanford model for circuit simulation. From measurements, the device-to-device (D2D) and cycle-to-cycle (C2C) statistical variation is extracted. In the low-resistive state (LRS) dispersion by D2D variability is dominant. In the high-resistive state
(HRS) C2C dispersion becomes the main source of fluctuation. A statistical procedure for the extraction of parameters of the compact model is presented. Thereby, in a circuit simulation the typical D2D and C2C fluctuations of the current–voltage (I-V) characteristics can be emulated by extracting statistical parameters of key model parameters. The statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of memory cells or can be used to emulate the synaptic behavior of these devices in artificial neural networks realized by a crossbar array of memristors.
KW - RRAM
KW - memristive device
KW - variability
Y1 - 2023
U6 - https://doi.org/10.1016/j.sse.2023.108606
SN - 0038-1101
VL - 201
ER -
TY - GEN
A1 - Perez-Bosch Quesada, Emilio
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Rizzi, Tommaso
A1 - Wen, Jianan
A1 - Ulbricht, Markus
A1 - Krstic, Milos
A1 - Wenger, Christian
A1 - Pérez, Eduardo
T1 - Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing
T2 - IEEE Transactions on Electron Devices
N2 - Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices’ nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.
KW - RRAM
KW - Vector Matrix Multiplication
KW - variability
Y1 - 2023
U6 - https://doi.org/10.1109/TED.2023.3244509
SN - 0018-9383
VL - 70
IS - 4
SP - 2009
EP - 2014
ER -
TY - GEN
A1 - Akhtar, Fatima
A1 - Dabrowski, Jaroslaw
A1 - Lukose, Rasuole
A1 - Wenger, Christian
A1 - Lukosius, Mindaugas
T1 - Chemical Vapor Deposition Growth of Graphene on 200 mm Ge (110)/Si Wafers and Ab Initio Analysis of Differences in Growth Mechanisms on Ge (110) and Ge (001)
T2 - ACS Applied Materials & Interfaces
N2 - For the fabrication of modern graphene devices, uniform growth of high-quality monolayer graphene on wafer scale is important. This work reports on the growth of large-scale graphene on semiconducting 8 inch Ge(110)/Si wafers by chemical vapor deposition and a DFT analysis of the growth process. Good graphene quality is indicated by the small FWHM (32 cm–1) of the Raman 2D band, low intensity ratio of the Raman D and G bands (0.06), and homogeneous SEM images and is confirmed by Hall measurements: high mobility (2700 cm2/Vs) and low sheet resistance (800 Ω/sq). In contrast to Ge(001), Ge(110) does not undergo faceting during the growth. We argue that Ge(001) roughens as a result of vacancy accumulation at pinned steps, easy motion of bonded graphene edges across (107) facets, and low energy cost to expand Ge area by surface vicinals, but on Ge(110), these mechanisms do not work due to different surface geometries and complex reconstruction.
KW - Graphene
KW - Chemical Vapor Deposition
Y1 - 2023
U6 - https://doi.org/10.1021/acsami.3c05860
SN - 1944-8244
VL - 15
IS - 30
SP - 36966
EP - 36974
ER -
TY - GEN
A1 - Rizzi, Tommaso
A1 - Baroni, Andrea
A1 - Glukhov, Artem
A1 - Bertozzi, Davide
A1 - Wenger, Christian
A1 - Ielmini, Daniele
A1 - Zambelli, Cristian
T1 - Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAs
T2 - IEEE Transactions on Device and Materials Reliability
N2 - Resistive Random Access Memory (RRAM) technology holds promises to improve the Field Programmable Gate Array (FPGA) performance, reduce the area footprint, and dramatically lower run-time energy requirements compared to the state-of-the-art CMOS-based products. However, the integration of RRAM in FPGAs is hindered by the high programming power consumption and by non-ideal behaviors of the device due to its stochastic nature that may overshadow the benefits in normal operation mode. To cope with these challenges, optimized programming strategies have to be investigated. In this work, we explore the impact that different procedures to set the device have on the run-time performance. Process, voltage, and temperature (PVT) variations as well as time-dependent drift effect of the RRAM device are considered in the assessment of 4T1R MUX designs characteristics. The comparison with tradition CMOS implementations reveals how the choice of the target resistive state and the programming algorithm are key design aspects to reduce the run-time delay and energy metrics, while at the same time improving the robustness against the different sources of variations.
KW - RRAM
KW - FPGA
Y1 - 2023
U6 - https://doi.org/10.1109/TDMR.2023.3259015
SN - 1530-4388
VL - 23
IS - 3
SP - 328
EP - 336
ER -
TY - GEN
A1 - Uhlmann, Max
A1 - Pérez-Bosch Quesada, Emilio
A1 - Fritscher, Markus
A1 - Pérez, Eduardo
A1 - Schubert, Markus Andreas
A1 - Reichenbach, Marc
A1 - Ostrovskyy, Philip
A1 - Wenger, Christian
A1 - Kahmen, Gerhard
T1 - One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing
T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS)
N2 - The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications.
KW - RRAM
KW - In-Memory Computing
Y1 - 2023
SN - 979-8-3503-0024-6
SN - 979-8-3503-0025-3
U6 - https://doi.org/10.1109/NEWCAS57931.2023.10198073
SN - 2474-9672
SN - 2472-467X
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
TY - GEN
A1 - Strobel, Carsten
A1 - Alvarado Chavarin, Carlos
A1 - Wenger, Christian
A1 - Albert, Matthias
A1 - Mikolajick, Thomas
T1 - Vertical Graphene-Based Transistors for Power Electronics, Optoelectronics and Radio-Frequency Applications
T2 - IEEE Nanotechnology Materials and Devices Conference (NMDC), Paestum, Italy, 22-25 October 2023
N2 - The combination of two-dimensional materials, such as graphene, with established thin films offers great opportunities for enabling next-generation vertical transistors for various applications. This paper gives a brief overview about different vertical transistor concepts using twodimensional materials proposed so far, e.g. the hot electron transistor and the Barristor. With the arrival of twodimensional materials, the hot electron transistor also experienced a revival with predicted cut-off frequencies in the THz range. The Barristor overcomes the weak current saturation of lateral graphene field-effect transistors and high on-off ratios up to 107 were demonstrated, which are suitable parameters for logic applications. By combining a
semiconductor-graphene-semiconductor design of the simplest hot electron transistor with the Barristor operating principle a new device, called graphene adjustable-barriers transistor, can be realized. This new device concept provides the potential for RF, power electronics, and optoelectronic applications.
KW - Graphene
Y1 - 2023
SN - 979-8-3503-3546-0
SN - 979-8-3503-3547-7
U6 - https://doi.org/10.1109/NMDC57951.2023.10344102
SN - 2473-0718
SP - 196
EP - 201
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
TY - GEN
A1 - Morales, Carlos
A1 - Mahmoodinezhad, Ali
A1 - Tschammer, Rudi
A1 - Kosto, Yuliia
A1 - Alvarado Chavarin, Carlos
A1 - Schubert, Markus Andreas
A1 - Wenger, Christian
A1 - Henkel, Karsten
A1 - Flege, Jan Ingo
T1 - Combination of Multiple Operando and In-Situ Characterization Techniques in a Single Cluster System for Atomic Layer Deposition: Unraveling the Early Stages of Growth of Ultrathin Al2O3 Films on Metallic Ti Substrates
T2 - Inorganics
N2 - This work presents a new ultra-high vacuum cluster tool to perform systematic studies of the early growth stages of atomic layer deposited (ALD) ultrathin films following a surface science approach. By combining operando (spectroscopic ellipsometry and quadrupole mass spectrometry) and in situ (X-ray photoelectron spectroscopy) characterization techniques, the cluster allows us to follow the evolution of substrate, film, and reaction intermediates as a function of the total number of ALD cycles, as well as perform a constant diagnosis and evaluation of the ALD process, detecting possible malfunctions that could affect the growth, reproducibility, and conclusions derived from data analysis. The homemade ALD reactor allows the use of multiple precursors and oxidants and its operation under pump and flow-type modes. To illustrate our experimental approach, we revisit the well-known thermal ALD growth of Al2O3 using trimethylaluminum and water. We deeply discuss the role of the metallic Ti thin film substrate at room temperature and 200 °C, highlighting the differences between the heterodeposition (<10 cycles) and the homodeposition (>10 cycles) growth regimes at both conditions. This surface science approach will benefit our understanding of the ALD process, paving the way toward more efficient and controllable manufacturing processes.
KW - Atomic layer deposition (ALD)
KW - in-situ
KW - operando
KW - X-ray photoelectron spectroscopy
KW - ellipsometry
KW - quadrupol mass spectrometry (QMS)
Y1 - 2023
U6 - https://doi.org/10.3390/inorganics11120477
SN - 2304-6740
VL - 11
IS - 12
ER -
TY - GEN
A1 - Capista, Daniele
A1 - Lukose, Rasuole
A1 - Majnoon, Farnaz
A1 - Lisker, Marco
A1 - Wenger, Christian
A1 - Lukosius, Mindaugas
T1 - Study on the metal -graphene contact resistance achieved with one -dimensional contact architecture
T2 - IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), Paestum, Italy, 22-25 October 2023
N2 - Graphene has always been considered as one of the materials with the greatest potential for the realization of improved microelectronic and photonic devices. But to actually reach its full potential in Si CMOS technology, graphene
-based devices need to overcome different challenges. They do not only
need to have better performances than standard devices, but they also need to be compatible with the production of standard Si based devices. To address the first challenge the main route requires the optimization of the contact resistance, that highly reduces the devices performance, while the second challenges requires the integration of graphene inside the standard production lines used for microelectronic. In this work we used an 8” wafer pilot -line to realize our devices and we studied the behavior of the contact resistance between metal and graphene obtained by one -dimensional contact architecture between the two materials. The contact resistance has been measured by means of Transmission Line Method (TLM) with several contact patterning.
KW - Graphene
Y1 - 2023
SN - 979-8-3503-3546-0
U6 - https://doi.org/10.1109/NMDC57951.2023.10343775
SP - 118
EP - 119
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
TY - GEN
A1 - Lukosius, Mindaugas
A1 - Lukose, Rasuolė
A1 - Lisker, Marco
A1 - Dubey, P. K.
A1 - Raju, A. I.
A1 - Capista, Daniele
A1 - Majnoon, Farnaz
A1 - Mai, A.
A1 - Wenger, Christian
T1 - Developments of Graphene devices in 200 mm CMOS pilot line
T2 - Proc. Nanotechnology Materials and Devices Conference (NMDC 2023),Paestum, Italy, 22-25 October 2023
N2 - Due to the unique electronic band structure, graphene has opened great potential to extend the functionality of a large variety of devices. Despite the significant progress in the fabrication of various graphene based microelectronic devices, the integration of graphene devices still lack the stability and compatibility with Si-technology processes. Therefore, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance. This study aims to explore various aspects of graphene research on a 200mm pilot line, with a focus on simulations and fabrication of graphene modulator. To be more precise, it includes design and fabrication of the layouts, necessary mask sets, creation of the flows, fabrication, and measurements of the Gr modulators on 200 mm wafers.
KW - Graphene
Y1 - 2023
SN - 979-8-3503-3546-0
U6 - https://doi.org/10.1109/NMDC57951.2023.10343569
SP - 505
EP - 506
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
TY - GEN
A1 - Maldonado, David
A1 - Cantudo, Antonio
A1 - Pérez, Eduardo
A1 - Romero-Zaliz, Rocio
A1 - Perez-Bosch Quesada, Emilio
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Jimenez-Molinos, Francisco
A1 - Wenger, Christian
A1 - Roldan, Juan Bautista
T1 - TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance
T2 - Frontiers in Neuroscience
N2 - We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics.
KW - RRAM
KW - Neural network
Y1 - 2023
U6 - https://doi.org/10.3389/fnins.2023.1271956
SN - 1662-4548
VL - 17
ER -
TY - GEN
A1 - Perez-Bosch Quesada, Emilio
A1 - Rizzi, Tommaso
A1 - Gupta, Aditya
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Schubert, Andreas
A1 - Pechmann, Stefan
A1 - Jia, Ruolan
A1 - Uhlmann, Max
A1 - Hagelauer, Amelie
A1 - Wenger, Christian
A1 - Pérez, Eduardo
T1 - Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing
T2 - 14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023
N2 - This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications.
Index Terms—radiation-hard, hardness-by-design, memristive
devices, Enclosed Layout Transistor, in-memory computing
KW - RRAM
Y1 - 2023
SN - 979-8-3503-0240-0
U6 - https://doi.org/10.1109/CDE58627.2023.10339525
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
TY - GEN
A1 - Pérez, Eduardo
A1 - Maldonado, David
A1 - Mahadevaiah, Mamathamba Kalishettyhalli
A1 - Perez-Bosch Quesada, Emilio
A1 - Cantudo, Antonio
A1 - Jimenez-Molinos, Francisco
A1 - Wenger, Christian
A1 - Roldan, Juan Bautista
T1 - A comparison of resistive switching parameters for memristive devices with HfO2 monolayers and Al2O3/HfO2 bilayers at the wafer scale
T2 - 14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023
N2 - Memristive devices integrated in 200 mm wafers
manufactured in 130 nm CMOS technology with two different
dielectrics, namely, a HfO2 monolayer and an Al2O3/HfO2 bilayer,
have been measured. The cycle-to-cycle (C2C) and device-todevice (D2D) variability have been analyzed at the wafer scale using different numerical methods to extract the set (Vset) and reset (Vreset) voltages. Some interesting differences between both technologies were found in terms of switching characteristics
KW - RRAM
Y1 - 2023
SN - 979-8-3503-0240-0
U6 - https://doi.org/10.1109/CDE58627.2023.10339417
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -
TY - GEN
A1 - Reiser, Daniel
A1 - Reichenbach, Marc
A1 - Rizzi, Tommaso
A1 - Baroni, Andrea
A1 - Fritscher, Markus
A1 - Wenger, Christian
A1 - Zambelli, Cristian
A1 - Bertozzi, Davide
T1 - Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations
T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom
N2 - In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate
multi-level conductance operation. The support of drift models
in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they
overlook key device- and array-level parameters affecting drift
resilience such as the programming algorithm of RRAM cells,
the choice of target conductance states and the weight-toconductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability.
KW - RRAM
Y1 - 2023
SN - 979-8-3503-0024-6
SN - 979-8-3503-0025-3
U6 - https://doi.org/10.1109/NEWCAS57931.2023
PB - IEEE
CY - Piscataway, NJ
ER -
TY - GEN
A1 - Franck, Max
A1 - Dabrowski, Jarek
A1 - Schubert, Markus Andreas
A1 - Vignaud, Dominique
A1 - Achehboune, Mohamed
A1 - Colomer, Jean‐François
A1 - Henrard, Luc
A1 - Wenger, Christian
A1 - Lukosius, Mindaugas
T1 - Investigating Impacts of Local Pressure and Temperature on CVD Growth of Hexagonal Boron Nitride on Ge(001)/Si
T2 - Advanced Materials Interfaces
N2 - AbstractThe chemical vapor deposition (CVD) growth of hexagonal boron nitride (hBN) on Ge substrates is a promising pathway to high‐quality hBN thin films without metal contaminations for microelectronic applications, but the effect of CVD process parameters on the hBN properties is not well understood yet. The influence of local changes in pressure and temperature due to different reactor configurations on the structure and quality of hBN films grown on Ge(001)/Si is studied. Injection of the borazine precursor close to the sample surface results in an inhomogeneous film thickness, attributed to an inhomogeneous pressure distribution at the surface, as shown by computational fluid dynamics simulations. The additional formation of nanocrystalline islands is attributed to unfavorable gas phase reactions due to the radiative heating of the injector. Both issues are mitigated by increasing the injector‐sample distance, leading to an 86% reduction in pressure variability on the sample surface and a 200 °C reduction in precursor temperature. The resulting hBN films exhibit no nanocrystalline islands, improved thickness homogeneity, and high crystalline quality (Raman FWHM = 23 cm−1). This is competitive with hBN films grown on other non‐metal substrates but achieved at lower temperature and with a low thickness of only a few nanometers.
KW - Boron Nitride
KW - 2D material
Y1 - 2025
U6 - https://doi.org/10.1002/admi.202400467
SN - 2196-7350
VL - 12
IS - 1
PB - Wiley
ER -
TY - GEN
A1 - Wen, Jianan
A1 - Vargas, Fabian Luis
A1 - Zhu, Fukun
A1 - Reiser, Daniel
A1 - Baroni, Andrea
A1 - Fritscher, Markus
A1 - Perez, Eduardo
A1 - Reichenbach, Marc
A1 - Wenger, Christian
A1 - Krstic, Milos
T1 - RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation
T2 - Microelectronics Reliability
N2 - The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current–voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector–matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments.
KW - RRAM
Y1 - 2025
U6 - https://doi.org/10.1016/j.microrel.2025.115630
SN - 0026-2714
VL - 168
SP - 1
EP - 10
PB - Elsevier BV
CY - Amsterdam
ER -