TY - GEN A1 - Petzold, Stefan A1 - Piros, Eszter A1 - Eilhardt, Robert A1 - Zintler, Alexander A1 - Vogel, Tobias A1 - Kaiser, Nico A1 - Radetinac, Aldin A1 - Komissinskiy, Philipp A1 - Jalaguier, Eric A1 - Nolot, Emmanuel A1 - Charpin-Nicolle, Christelle A1 - Wenger, Christian A1 - Molina-Luna, Leopoldo A1 - Miranda, Enrique A1 - Alff, Lambert T1 - Tailoring the Switching Dynamics in Yttrium Oxide-Based RRAM Devices by Oxygen Engineering: From Digital to Multi-Level Quantization toward Analog Switching T2 - Advanced Electronic Materials N2 - This work investigates the transition from digital to gradual or analog resistive switching in yttrium oxide‐based resistive random‐access memory devices. It is shown that this transition is determined by the amount of oxygen in the functional layer. A homogeneous reduction of the oxygen content not only reduces the electroforming voltage, allowing for forming‐free devices, but also decreases the voltage operation window of switching, thereby reducing intra‐device variability. The most important effect as the dielectric becomes substoichiometric by oxygen engineering is that more intermediate (quantized) conduction states are accessible. A key factor for this reproducibly controllable behavior is the reduced local heat dissipation in the filament region due to the increased thermal conductivity of the oxygen depleted layer. The improved accessibility of quantized resistance states results in a semi‐gradual switching both for the set and reset processes, as strongly desired for multi‐bit storage and for an accurate definition of the synaptic weights in neuromorphic systems. A theoretical model based on the physics of mesoscopic structures describing current transport through a nano‐constriction including asymmetric potential drops at the electrodes and non‐linear conductance quantization is provided. The results contribute to a deeper understanding on how to tailor materials properties for novel memristive functionalities. KW - RRAM KW - Multilevel switching Y1 - 2020 U6 - https://doi.org/10.1002/aelm.202000439 SN - 2199-160X VL - 6 IS - 11 ER - TY - GEN A1 - Perez-Avila, Antonio Javier A1 - Gonzalez-Cordero, Gerardo A1 - Pérez, Eduardo A1 - Perez-Bosch Quesada, Emilio A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Wenger, Christian A1 - Roldan, Juan Bautista A1 - Jimenez-Molinos, Francisco T1 - Behavioral modeling of multilevel HfO2-based memristors for neuromorphic circuit simulation T2 - XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain N2 - An artificial neural network based on resistive switching memristors is implemented and simulated in LTspice. The influence of memristor variability and the reduction of the continuous range of synaptic weights into a discrete set of conductance levels is analyzed. To do so, a behavioral model is proposed for multilevel resistive switching memristors based on Al-doped HfO2 dielectrics, and it is implemented in a spice based circuit simulator. The model provides an accurate description of the conductance in the different conductive states in addition to describe the device-to-device variability KW - RRAM KW - Multilevel switching KW - behavorial model Y1 - 2020 U6 - https://doi.org/10.1109/DCIS51330.2020.9268652 ER - TY - GEN A1 - Pérez, Eduardo A1 - Ossorio, Óscar G. A1 - Dueñas, Salvador A1 - Castán, Helena A1 - García, Hector A1 - Wenger, Christian T1 - Programming Pulse Width Assessment for Reliable and Low-Energy Endurance Performance in Al:HfO2-Based RRAM Arrays T2 - Electronics (MDPI) N2 - A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 μ s and 50 ns and assessed on Al-doped HfO 2 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 μ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 μ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width KW - RRAM KW - Reliability Y1 - 2020 U6 - https://doi.org/10.3390/electronics9050864 SN - 2079-9292 VL - 9 IS - 5 ER - TY - GEN A1 - Morales, Carlos A1 - Mahmoodinezhad, Ali A1 - Schubert, Andreas Markus A1 - Wenger, Christian A1 - Henkel, Karsten A1 - Flege, Jan Ingo T1 - Functional ultra-thin oxide films deposited by atomic layer deposition on structured substrates T2 - Verhandlungen der DPG - SurfaceScience21 N2 - In the last decades, atomic layer deposition (ALD) has gained prominence in the materials and surface science communities owing to its high potential for integration as a scalable process in microelectronics. ALD's largest strengths are its well-controlled layer-by-layer deposition and growth conformity on 3D structures. Yet, the ALD technique is also well known to lead to amorphous and defective, non-stoichiometric thin films, resulting in modified materials properties that may even preferentially be used in certain applications. To study these issues, we have developed an in-situ ALD reactor attached to an X-ray photoelectron spectroscopy (XPS) system, capable of switching between both pump and flow-type operation. This novel tool allows to cover the entire range of compounds and recipes used in ALD, thus clarifying the role of such defects at different deposition stages, growth conditions and film/substrate interfaces. To exemplify these sorts of studies, we show the deposition of Al2O3 5-10 nm films on nanostructured Si, and their use as substrates for functional CeOx ALD deposits. KW - Atomic layer deposition KW - sensors KW - structured substrates KW - in-situ X-ray photoelectron spectroscopy Y1 - 2021 UR - https://www.dpg-verhandlungen.de/year/2021/conference/surfacescience/part/o/session/74/contribution/5 VL - 2021 PB - Deutsche Physikalische Gesellschaft e.V. CY - Bad Honnef ER - TY - GEN A1 - Pérez-Bosch Quesada, Emilio A1 - Romero-Zaliz, Rocío A1 - Pérez, Eduardo A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Reuben, John A1 - Schubert, Markus Andreas A1 - Jiménez-Molinos, Francisco A1 - Roldán, Juan Bautista A1 - Wenger, Christian T1 - Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems T2 - Electronics (MDPI) N2 - In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study. KW - RRAM KW - multilevel switching KW - compact modeling KW - Verilog-A Y1 - 2021 U6 - https://doi.org/10.3390/electronics10060645 SN - 2079-9292 VL - 10 IS - 6 ER - TY - GEN A1 - Pechmann, Stefan A1 - Mai, Timo A1 - Völkel, Matthias A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Pérez, Eduardo A1 - Perez-Bosch Quesada, Emilio A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Hagelauer, Amelie T1 - A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells T2 - Electronics N2 - In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9. KW - RRAM KW - Multilevel switching KW - Programming circuit Y1 - 2021 U6 - https://doi.org/10.3390/electronics10050530 SN - 2079-9292 VL - 10 IS - 5 ER - TY - GEN A1 - Matbaechi Ettehad, Honeyeh A1 - Wenger, Christian T1 - Characterization and Separation of Live and Dead Yeast Cells Using CMOS-Based DEP Microfluidics T2 - Micromachines N2 - This study aims at developing a miniaturized CMOS integrated silicon-based microfluidic system, compatible with a standard CMOS process, to enable the characterization, and separation of live and dead yeast cells (as model bio-particle organisms) in a cell mixture using the DEP technique. DEP offers excellent benefits in terms of cost, operational power, and especially easy electrode integration with the CMOS architecture, and requiring label-free sample preparation. This can increase the likeliness of using DEP in practical settings. In this work the DEP force was generated using an interdigitated electrode arrays (IDEs) placed on the bottom of a CMOS-based silicon microfluidic channel. This system was primarily used for the immobilization of yeast cells using DEP. This study validated the system for cell separation applications based on the distinct responses of live and dead cells and their surrounding media. The findings confirmed the device’s capability for efficient, rapid and selective cell separation. The viability of this CMOS embedded microfluidic for dielectrophoretic cell manipulation applications and compatibility of the dielectrophoretic structure with CMOS production line and electronics, enabling its future commercially mass production. KW - dielectrophoresis KW - microfluidics KW - cell characterization KW - CMOS Y1 - 2021 U6 - https://doi.org/10.3390/mi12030270 SN - 2072-666X VL - 12 IS - 3 ER - TY - GEN A1 - Pérez, Eduardo A1 - Pérez-Ávila, Antonio Javier A1 - Romero-Zaliz, Rocío A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Pérez-Bosch Quesada, Emilio A1 - Roldan, Juan Bautista A1 - Jiménez-Molinos, Francisco A1 - Wenger, Christian T1 - Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing T2 - Electronics (MDPI) N2 - Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8×8 vector-matrixmultiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters. KW - RRAM KW - Multilevel switching KW - In-memory computing Y1 - 2021 U6 - https://doi.org/10.3390/electronics10091084 SN - 2079-9292 VL - 10 IS - 9 ER - TY - GEN A1 - Milo, Valerio A1 - Anzalone, Francesco A1 - Zambelli, Cristian A1 - Pérez, Eduardo A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Ossorio, Óscar G. A1 - Olivo, Piero A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - Optimized programming algorithms for multilevel RRAM in hardware neural networks T2 - IEEE International Reliability Physics Symposium (IRPS), 2021 N2 - A key requirement for RRAM in neural network accelerators with a large number of synaptic parameters is the multilevel programming. This is hindered by resistance imprecision due to cycle-to-cycle and device-to-device variations. Here, we compare two multilevel programming algorithms to minimize resistance variations in a 4-kbit array of HfO 2 RRAM. We show that gate-based algorithms have the highest reliability. The optimized scheme is used to implement a neural network with 9-level weights, achieving 91.5% (vs. software 93.27%) in MNIST recognition. KW - RRAM KW - Multilevel switching KW - neural network KW - memristive switching Y1 - 2021 SN - 978-1-7281-6894-4 U6 - https://doi.org/10.1109/IRPS46558.2021.9405119 SN - 1938-1891 ER - TY - GEN A1 - Petryk, Dmytro A1 - Dyka, Zoya A1 - Pérez, Eduardo A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Kabin, Ievgen A1 - Wenger, Christian A1 - Langendörfer, Peter T1 - Evaluation of the Sensitivity of RRAM Cells to Optical Fault Injection Attacks T2 - EUROMICRO Conference on Digital System Design (DSD 2020), Special Session: Architecture and Hardware for Security Applications (AHSA) Y1 - 2021 SN - 978-1-7281-9535-3 U6 - https://doi.org/10.1109/DSD51259.2020.00047 SN - 978-1-7281-9536-0 ER -