TY - GEN A1 - Capella, Fernanda M. A1 - Brandalero, Marcelo A1 - Junior, Jair Fajardo A1 - Beck, Antonio Carlos Schneider A1 - Carro, Luigi T1 - A Multiple-ISA Reconfigurable Architecture T2 - 2013 III Brazilian Symposium on Computing Systems Engineering (SBESC), Dec. 4 2013 to Dec. 8 2013, Niteroi, Rio De Janeiro, Brazil Y1 - 2013 U6 - https://doi.org/10.1109/SBESC.2013.23 VL - 1 SP - 71 EP - 76 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Souto, Thiago Dadalt A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - Predicting performance in multi-core systems with shared reconfigurable accelerators T2 - Journal of Systems Architecture Y1 - 2019 U6 - https://doi.org/10.1016/j.sysarc.2019.07.010 SN - 1383-7621 VL - 98 SP - 201 EP - 213 PB - Elsevier ER - TY - GEN A1 - Brandalero, Marcelo A1 - Shafique, Muhammad A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration T2 - 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) Y1 - 2019 SN - 978-3-9819263-2-3 SN - 978-3-9819263-3-0 SN - 978-1-7281-0331-0 U6 - https://doi.org/10.23919/DATE.2019.8715121 SN - 1558-1101 SN - 1530-1591 SP - 582 EP - 585 ER - TY - GEN A1 - Oliveira, Geraldo Francisco A1 - Gonçalves, Larissa Rozales A1 - Brandalero, Marcelo A1 - Beck, Antonio Carlos Schneider A1 - Carro, Luigi T1 - Employing classification-based algorithms for general-purpose approximate computing T2 - 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Y1 - 2018 SN - 978-1-5386-4114-9 SN - 978-1-5386-4115-6 U6 - https://doi.org/10.1109/DAC.2018.8465822 SP - 70:1 EP - 70:6 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider A1 - Shafique, Muhammad T1 - Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applications T2 - 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Y1 - 2018 SN - 978-1-5386-4114-9 SN - 978-1-5386-4115-6 U6 - https://doi.org/10.1109/DAC.2018.8465930 SP - 160:1 EP - 160:6 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Malfatti, Guilherme Meneguzzi A1 - Oliveira, Geraldo Francisco A1 - Silveira, Leonardo Almeida da A1 - Gonçalves, Larissa Rozales A1 - Da Silva, Bruno Castro A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - Efficient Local Memory Support for Approximate Computing T2 - 2018 VIII Brazilian Symposium on Computing Systems Engineering (SBESC) Y1 - 2018 SN - 978-1-7281-0240-5 SN - 978-1-7281-0241-2 U6 - https://doi.org/10.1109/SBESC.2018.00026 SN - 2324-7894 SN - 2324-7886 SP - 122 EP - 129 ER - TY - GEN A1 - Capella, Fernanda M. A1 - Brandalero, Marcelo A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - A multiple-ISA reconfigurable architecture T2 - Special Issue on “Selected papers from the 2013 Brazilian Symposium on Computing Systems Engineering (SBESC 2013)” Y1 - 2016 SN - 0929-5585 SN - 1572-8080 VL - 19 IS - 4 SP - 329 EP - 344 ER - TY - GEN A1 - Fernandes dos Santos, Fernando A1 - Brandalero, Marcelo A1 - Rech Junior, Rubens Luiz A1 - Hübner, Michael A1 - Rech, Paolo A1 - Sullivan, Michael A1 - Martins Basso, Pedro A1 - Carro, Luigi T1 - Reduced Precision DWC: an Efficient Hardening Strategy for Mixed-Precision Architectures T2 - IEEE Transactions on Computers N2 - Duplication with Comparison (DWC) is an effective software-level solution to improve the reliability of computing devices. However, it introduces significant performance and energy consumption overheads that could render the protected application unsuitable for high-performance computing or real-time safety-critical applications. Modern computing architectures offer the possibility to execute operations in various precisions, and recent NVIDIA GPUs even feature dedicated functional units for computing with programmable accuracy. In this work, we propose Reduced-Precision Duplication with Comparison (RP-DWC) as a means to leverage the available mixed-precision hardware resources to implement software-level fault detection with reduced overheads. We discuss the benefits and challenges associated with RP-DWC and show that the intrinsic difference between the mixed-precision copies allows for the detection of most, but not all, errors. However, as the undetected faults are the ones that fall into the difference between precisions, they are the ones that produce a much smaller impact in the application output. We investigate, through fault injection and beam experiment campaigns, using three microbenchmarks and two real applications on Volta GPUs, RP-DWC impact into fault detection, performance, and energy consumption. We show that RP-DWC achieves an excellent coverage (up to 86%) with minimal overheads (0.1% time and 24% energy consumption overhead). Y1 - 2021 U6 - https://doi.org/10.1109/TC.2021.3058872 SN - 0018-9340 VL - 71(2022) IS - 3 SP - 573 EP - 586 ER - TY - GEN A1 - Exenberger Becker, Pedro H. A1 - Sartor, Anderson L. A1 - Brandalero, Marcelo A1 - Jost, Tiago Trevisan A1 - Wong, Stephan A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings Y1 - 2018 SN - 978-3-319-78889-0 SN - 978-3-319-78890-6 U6 - https://doi.org/10.1007/978-3-319-78890-6_40 SN - 0302-9743 SN - 1611-3349 SP - 499 EP - 510 PB - Springer CY - Cham ER - TY - GEN A1 - Brandalero, Marcelo A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider A1 - Shafique, Muhammad T1 - Multi-Target Adaptive Reconfigurable Acceleration for Low-Power IoT Processing T2 - IEEE Transactions on Computers Y1 - 2020 U6 - https://doi.org/10.1109/TC.2020.2984736 SN - 0018-9340 SN - 1557-9956 ER -