TY - CHAP A1 - Bertozzi, Davide A1 - Strano, A. A1 - Ludovici, D. A1 - Pavlidis, V. A1 - Angiolini, F. A1 - Krstic, Milos T1 - The Synchronization Challenge Y1 - 2010 ER - TY - GEN A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Glukhov, Artem A1 - Bertozzi, Davide A1 - Wenger, Christian A1 - Ielmini, Daniele A1 - Zambelli, Cristian T1 - Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAs T2 - IEEE Transactions on Device and Materials Reliability N2 - Resistive Random Access Memory (RRAM) technology holds promises to improve the Field Programmable Gate Array (FPGA) performance, reduce the area footprint, and dramatically lower run-time energy requirements compared to the state-of-the-art CMOS-based products. However, the integration of RRAM in FPGAs is hindered by the high programming power consumption and by non-ideal behaviors of the device due to its stochastic nature that may overshadow the benefits in normal operation mode. To cope with these challenges, optimized programming strategies have to be investigated. In this work, we explore the impact that different procedures to set the device have on the run-time performance. Process, voltage, and temperature (PVT) variations as well as time-dependent drift effect of the RRAM device are considered in the assessment of 4T1R MUX designs characteristics. The comparison with tradition CMOS implementations reveals how the choice of the target resistive state and the programming algorithm are key design aspects to reduce the run-time delay and energy metrics, while at the same time improving the robustness against the different sources of variations. KW - RRAM KW - FPGA Y1 - 2023 U6 - https://doi.org/10.1109/TDMR.2023.3259015 SN - 1530-4388 VL - 23 IS - 3 SP - 328 EP - 336 ER - TY - CHAP A1 - Krstic, Milos A1 - Fan, X. A1 - Grass, Eckhard A1 - Strano, A. A1 - Bertozzi, Davide A1 - Heer, Ch. A1 - Sanders, B. A1 - Benini, L. A1 - Kakooe, M. R. T1 - Moonrake Chip - GALS Demonstrator in 40 nm CMOS Technology Y1 - 2011 ER - TY - GEN A1 - Reiser, Daniel A1 - Reichenbach, Marc A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Wenger, Christian A1 - Zambelli, Cristian A1 - Bertozzi, Davide T1 - Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom N2 - In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate multi-level conductance operation. The support of drift models in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they overlook key device- and array-level parameters affecting drift resilience such as the programming algorithm of RRAM cells, the choice of target conductance states and the weight-toconductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability. KW - RRAM Y1 - 2023 SN - 979-8-3503-0024-6 SN - 979-8-3503-0025-3 U6 - https://doi.org/10.1109/NEWCAS57931.2023 PB - IEEE CY - Piscataway, NJ ER -