TY - GEN A1 - Korol, Guilherme dos Santos A1 - Jordan, Michael Guilherme A1 - Brandalero, Marcelo A1 - Rutzig, Mateus Beck A1 - Beck, Antonio Carlos Schneider T1 - Power-Aware Phase Oriented Reconfigurable Architecture T2 - 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Y1 - 2019 SN - 978-1-7281-0996-1 SN - 978-1-7281-0997-8 U6 - https://doi.org/10.1109/ICECS46596.2019.8965011 SP - 626 EP - 629 ER - TY - GEN A1 - Korol, Guilherme dos Santos A1 - Jordan, Michael Guilherme A1 - Silva, Raul Silveira A1 - Pereira, Monica Magalhães A1 - Brandalero, Marcelo A1 - Rutzig, Mateus Beck A1 - Beck, Antonio Carlos Schneider T1 - A Runtime Power-Aware Phase Predictor for CGRAs T2 - 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig) Y1 - 2019 SN - 978-1-7281-1957-1 SN - 978-1-7281-1958-8 U6 - https://doi.org/10.1109/ReConFig48160.2019.8994802 SN - 2640-0472 SN - 2325-6532 SP - 1 EP - 8 ER - TY - GEN A1 - Silva, Raul A1 - Korol, Guilherme dos Santos A1 - Jordan, Michael Guilherme A1 - Brandalero, Marcelo A1 - Hübner, Michael A1 - Pereira, Monica A1 - Rutzig, Mateus Beck A1 - Beck, Antonio Carlos Schneider T1 - A Management Technique for Concurrent Access to a Reconfigurable Accelerator T2 - 33rd Symposium on Integrated Circuits and Systems Design (SBCCI) Y1 - 2020 SN - 978-1-7281-9625-1 SN - 978-1-7281-9626-8 U6 - https://doi.org/10.1109/SBCCI50935.2020.9189927 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Souto, Thiago Dadalt A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - Predicting performance in multi-core systems with shared reconfigurable accelerators T2 - Journal of Systems Architecture Y1 - 2019 U6 - https://doi.org/10.1016/j.sysarc.2019.07.010 SN - 1383-7621 VL - 98 SP - 201 EP - 213 PB - Elsevier ER - TY - GEN A1 - Brandalero, Marcelo A1 - Shafique, Muhammad A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration T2 - 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) Y1 - 2019 SN - 978-3-9819263-2-3 SN - 978-3-9819263-3-0 SN - 978-1-7281-0331-0 U6 - https://doi.org/10.23919/DATE.2019.8715121 SN - 1558-1101 SN - 1530-1591 SP - 582 EP - 585 ER - TY - GEN A1 - Cardoso, Douglas Maciel A1 - Tonetto, Rafael Billig A1 - Brandalero, Marcelo A1 - Agostini, Luciano A1 - Nazar, Gabriel L. A1 - Azambuja, José Rodrigo A1 - Beck, Antonio Carlos Schneider T1 - Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors T2 - 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Y1 - 2019 SN - 978-1-7281-0996-1 SN - 978-1-7281-0997-8 U6 - https://doi.org/10.1109/ICECS46596.2019.8964749 SP - 201 EP - 204 ER - TY - GEN A1 - Tonetto, Rafael Billig A1 - Cardoso, Douglas Maciel A1 - Brandalero, Marcelo A1 - Agostini, Luciano A1 - Nazar, Gabriel L. A1 - Azambuja, José Rodrigo A1 - Beck, Antonio Carlos Schneider T1 - A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors T2 - 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC) Y1 - 2019 SN - 978-1-7281-3915-9 SN - 978-1-7281-3916-6 U6 - https://doi.org/10.1109/VLSI-SoC.2019.8920350 SN - 2324-8440 SN - 2324-8432 SP - 287 EP - 292 ER - TY - GEN A1 - Exenberger Becker, Pedro H. A1 - Sartor, Anderson L. A1 - Brandalero, Marcelo A1 - Beck, Antonio Carlos Schneider T1 - BRAM-based function reuse for multi-core architectures in FPGAs T2 - Microprocessors and Microsystems Y1 - 2019 U6 - https://doi.org/10.1016/j.micpro.2018.09.007 SN - 0141-9331 VL - 63 SP - 237 EP - 248 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Silveira, Leonardo Almeida da A1 - Souza, Jeckson Dellagostin de A1 - Beck, Antonio Carlos Schneider T1 - Accelerating error-tolerant applications with approximate function reuse T2 - Science of Computer Programming Y1 - 2019 U6 - https://doi.org/10.1016/j.scico.2017.05.003 SN - 0167-6423 VL - 165 SP - 54 EP - 67 ER - TY - GEN A1 - Exenberger Becker, Pedro H. A1 - Sartor, Anderson L. A1 - Brandalero, Marcelo A1 - Jost, Tiago Trevisan A1 - Wong, Stephan A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs T2 - Applied Reconfigurable Computing. Architectures, Tools, and Applications 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings Y1 - 2018 SN - 978-3-319-78889-0 SN - 978-3-319-78890-6 U6 - https://doi.org/10.1007/978-3-319-78890-6_40 SN - 0302-9743 SN - 1611-3349 SP - 499 EP - 510 PB - Springer CY - Cham ER - TY - GEN A1 - Oliveira, Geraldo Francisco A1 - Gonçalves, Larissa Rozales A1 - Brandalero, Marcelo A1 - Beck, Antonio Carlos Schneider A1 - Carro, Luigi T1 - Employing classification-based algorithms for general-purpose approximate computing T2 - 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Y1 - 2018 SN - 978-1-5386-4114-9 SN - 978-1-5386-4115-6 U6 - https://doi.org/10.1109/DAC.2018.8465822 SP - 70:1 EP - 70:6 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider A1 - Shafique, Muhammad T1 - Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applications T2 - 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Y1 - 2018 SN - 978-1-5386-4114-9 SN - 978-1-5386-4115-6 U6 - https://doi.org/10.1109/DAC.2018.8465930 SP - 160:1 EP - 160:6 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Malfatti, Guilherme Meneguzzi A1 - Oliveira, Geraldo Francisco A1 - Silveira, Leonardo Almeida da A1 - Gonçalves, Larissa Rozales A1 - Da Silva, Bruno Castro A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - Efficient Local Memory Support for Approximate Computing T2 - 2018 VIII Brazilian Symposium on Computing Systems Engineering (SBESC) Y1 - 2018 SN - 978-1-7281-0240-5 SN - 978-1-7281-0241-2 U6 - https://doi.org/10.1109/SBESC.2018.00026 SN - 2324-7894 SN - 2324-7886 SP - 122 EP - 129 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Beck, Antonio Carlos Schneider T1 - A Mechanism for energy-efficient reuse of decoding and scheduling of x86 instruction streams T2 - Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 Y1 - 2017 SN - 978-3-9815370-8-6 SN - 978-3-9815370-9-3 SN - 978-1-5090-5826-6 U6 - https://doi.org/10.23919/DATE.2017.7927223 SN - 1558-1101 SP - 1468 EP - 1473 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Beck, Antonio Carlos Schneider T1 - Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism T2 - Special Issue on “SBESC Embedded Systems 2014” Y1 - 2016 U6 - https://doi.org/10.1007/s10617-016-9174-4 SN - 0929-5585 SN - 1572-8080 VL - 20 IS - 2 SP - 155 EP - 169 ER - TY - GEN A1 - Silveira, Leonardo Almeida da A1 - Brandalero, Marcelo A1 - Souza, Jeckson Dellagostin de A1 - Beck, Antonio Carlos Schneider T1 - The Potential of Accelerating Image-Processing Applications by Using Approximate Function Reuse T2 - 2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC) Y1 - 2016 SN - 978-1-5090-2653-1 SN - 978-1-5090-2654-8 U6 - https://doi.org/10.1109/SBESC.2016.026 SN - 2324-7894 SP - 122 EP - 127 ER - TY - GEN A1 - Capella, Fernanda M. A1 - Brandalero, Marcelo A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider T1 - A multiple-ISA reconfigurable architecture T2 - Special Issue on “Selected papers from the 2013 Brazilian Symposium on Computing Systems Engineering (SBESC 2013)” Y1 - 2016 SN - 0929-5585 SN - 1572-8080 VL - 19 IS - 4 SP - 329 EP - 344 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Beck, Antonio Carlos Schneider T1 - Potential of Using a Reconfigurable System on a Superscalar Core for ILP Improvements T2 - 2014 Brazilian Symposium on Computing Systems Engineering Y1 - 2014 SN - 978-1-4799-8559-3 U6 - https://doi.org/10.1109/SBESC.2014.19 SN - 2324-7894 SN - 2324-7886 SP - 43 EP - 48 ER - TY - GEN A1 - Capella, Fernanda M. A1 - Brandalero, Marcelo A1 - Junior, Jair Fajardo A1 - Beck, Antonio Carlos Schneider A1 - Carro, Luigi T1 - A Multiple-ISA Reconfigurable Architecture T2 - 2013 III Brazilian Symposium on Computing Systems Engineering (SBESC), Dec. 4 2013 to Dec. 8 2013, Niteroi, Rio De Janeiro, Brazil Y1 - 2013 U6 - https://doi.org/10.1109/SBESC.2013.23 VL - 1 SP - 71 EP - 76 ER - TY - GEN A1 - Brandalero, Marcelo A1 - Carro, Luigi A1 - Beck, Antonio Carlos Schneider A1 - Shafique, Muhammad T1 - Multi-Target Adaptive Reconfigurable Acceleration for Low-Power IoT Processing T2 - IEEE Transactions on Computers Y1 - 2020 U6 - https://doi.org/10.1109/TC.2020.2984736 SN - 0018-9340 SN - 1557-9956 ER - TY - GEN A1 - Medeiros, Thiarles S. A1 - Berned, Gustavo P. A1 - Navarro, Antoni A1 - Rossi, Fábio D. A1 - Luizelli, Marcelo C. A1 - Brandalero, Marcelo A1 - Hübner, Michael A1 - Beck, Antonio Carlos Schneider A1 - Lorenzon, Arthur F. T1 - Aging-Aware Parallel Execution T2 - IEEE Embedded System Letters Y1 - 2020 U6 - https://doi.org/10.1109/LES.2020.3021854 SN - 1943-0663 VL - 13 (2021) IS - 3 SP - 122 EP - 125 ER -