TY - GEN A1 - Baroni, Andrea A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Pérez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - Tackling the Low Conductance State Drift through Incremental Reset and Verify in RRAM Arrays T2 - 2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021 N2 - Resistive switching memory (RRAM) is a promising technology for highly efficient computing scenarios. RRAM arrays enabled the acceleration of neural networks for artificial intelligence and the creation of In-Memory Computing circuits. However, the arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation in those applications. Among those, one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are fundamental for an accurate Multi-level conductance operation. In this work, we tackle the issue by developing an Incremental Reset and Verify technique showing enhanced variability and reliability features compared with a traditional refresh-based approach. KW - RRAM KW - resistive switching KW - neural network Y1 - 2021 SN - 978-1-6654-1794-5 SN - 978-1-6654-1795-2 U6 - https://doi.org/10.1109/IIRW53245.2021.9635613 SN - 2374-8036 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Mannocci, Piergiulio A1 - Baroni, Andrea A1 - Melacarne, Enrico A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Pérez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - In-Memory Principal Component Analysis by Crosspoint Array of Rresistive Switching Memory T2 - IEEE Nanotechnology Magazine N2 - In Memory Computing (IMC) is one of the most promising candidates for data-intensive computing accelerators of machine learning (ML). A key ML algorithm for dimensionality reduction and classification is principal component analysis (PCA), which heavily relies on matrixvector multiplications (MVM) for which classic von Neumann architectures are not optimized. Here, we provide the experimental demonstration of a new IMCbased PCA algorithm based on power iteration and deflation executed in a 4-kbit array of resistive switching random-access memory (RRAM). The classification accuracy of the Wisconsin Breast Cancer data set reaches 95.43%, close to floatingpoint implementation. Our simulations indicate a 250× improvement in energy efficiency compared to commercial GPUs, thus supporting IMC for energy-efficient ML in modern data-intensive computing. KW - RRAM KW - Multilevel switching KW - neural network Y1 - 2022 U6 - https://doi.org/10.1109/MNANO.2022.3141515 SN - 1932-4510 VL - 16 IS - 2 SP - 4 EP - 13 ER - TY - GEN A1 - Glukhov, Artem A1 - Milo, Valerio A1 - Baroni, Andrea A1 - Lepri, Nicola A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Pérez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators T2 - 2022 IEEE International Reliability Physics Symposium (IRPS) N2 - Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators. KW - RRAM KW - Multilevel switching KW - neural network Y1 - 2022 SN - 978-1-6654-7950-9 SN - 978-1-6654-7951-6 U6 - https://doi.org/10.1109/IRPS48227.2022.9764497 SN - 2473-2001 SP - 3C.3-1 EP - 3C.3-7 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Baroni, Andrea A1 - Glukhov, Artem A1 - Pérez, Eduardo A1 - Wenger, Christian A1 - Calore, Enrico A1 - Schifano, Sebastiano Fabio A1 - Olivo, Piero A1 - Ielmini, Daniele A1 - Zambelli, Cristian T1 - An energy-efficient in-memory computing architecture for survival data analysis based on resistive switching memories T2 - Frontiers in Neuroscience N2 - One of the objectives fostered in medical science is the so-called precision medicine, which requires the analysis of a large amount of survival data from patients to deeply understand treatment options. Tools like Machine Learning and Deep Neural Networks are becoming a de-facto standard. Nowadays, computing facilities based on the Von Neumann architecture are devoted to these tasks, yet rapidly hitting a bottleneck in performance and energy efficiency. The In-Memory Computing (IMC) architecture emerged as a revolutionary approach to overcome that issue. In this work, we propose an IMC architecture based on Resistive switching memory (RRAM) crossbar arrays to provide a convenient primitive for matrix–vector multiplication in a single computational step. This opens massive performance improvement in the acceleration of a neural network that is frequently used in survival analysis of biomedical records, namely the DeepSurv. We explored how the synaptic weights mapping strategy and the programming algorithms developed to counter RRAM non-idealities expose a performance/energy trade-off. Finally, we assessed the benefits of the proposed architectures with respect to a GPU-based realization of the same task, evidencing a tenfold improvement in terms of performance and three orders of magnitude with respect to energy efficiency. KW - RRAM KW - In-Memory Computing KW - Multilevel switching Y1 - 2022 U6 - https://doi.org/10.3389/fnins.2022.932270 SN - 1662-4548 VL - Vol. 16 SP - 1 EP - 16 ER - TY - GEN A1 - Baroni, Andrea A1 - Glukhov, Artem A1 - Pérez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele A1 - Olivo, Piero A1 - Zambelli, Cristian T1 - Low Conductance State Drift Characterization and Mitigation in Resistive Switching Memories (RRAM) for Artificial Neural Networks T2 - IEEE Transactions on Device and Materials Reliability N2 - The crossbar structure of Resistive-switching random access memory (RRAM) arrays enabled the In-Memory Computing circuits paradigm, since they imply the native acceleration of a crucial operations in this scenario, namely the Matrix-Vector-Multiplication (MVM). However, RRAM arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation. A critical one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are mandatory for an accurate multi-level conductance operation. In this work, we analyze the benefits of a new programming algorithm that embodies Set and Reset switching operations to achieve better conductance control and lower variability. Data retention analysis performed with different temperatures for 168 hours evidence its superior performance with respect to standard programming approach. Finally, we explored the benefits of using our methodology at a higher abstraction level, through the simulation of an Artificial Neural Network for image recognition task (MNIST dataset). The accuracy achieved shows higher performance stability over temperature and time. KW - RRAM KW - neural network KW - Multilevel switching Y1 - 2022 U6 - https://doi.org/10.1109/TDMR.2022.3182133 SN - 1530-4388 VL - 22 IS - 3 SP - 340 EP - 347 ER - TY - GEN A1 - Glukhov, Artem A1 - Lepri, Nicola A1 - Milo, Valerio A1 - Baroni, Andrea A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Pérez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays T2 - Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022) N2 - Resistive-switching random access memory (RRAM) is a promising technology that enables advanced applications in the field of in-memory computing (IMC). By operating the memory array in the analogue domain, RRAM-based IMC architectures can dramatically improve the energy efficiency of deep neural networks (DNNs). However, achieving a high inference accuracy is challenged by significant variation of RRAM conductance levels, which can be compensated by (i) advanced programming techniques and (ii) variability-aware training (VAT) algorithms. In both cases, however, detailed knowledge and accurate physics-based statistical models of RRAM are needed to develop programming and VAT methodologies. This work presents an end-to-end approach to the development of highly-accurate IMC circuits with RRAM, encompassing the device modeling, the precise programming algorithm, and the VAT simulations to maximize the DNN classification accuracy in presence of conductance variations. KW - RRAM KW - HfO2 KW - neural network KW - memristive switching Y1 - 2022 U6 - https://doi.org/10.1109/VLSI-SoC54400.2022.9939653 SP - 1 EP - 5 ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Pérez, Eduardo A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages T2 - 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) N2 - RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states. KW - RRAM KW - Multilevel switching KW - AI accelarator Y1 - 2022 SN - 978-1-6654-5938-9 SN - 978-1-6654-5937-2 U6 - https://doi.org/10.1109/DFT56152.2022.9962345 SN - 2765-933X SP - 1 EP - 6 ER - TY - GEN A1 - Nikiruy, Kristina A1 - Pérez, Eduardo A1 - Baroni, Andrea A1 - Dorai Swamy Reddy, Keerthi A1 - Pechmann, Stefan A1 - Wenger, Christian A1 - Ziegler, Martin T1 - Blooming and pruning: learning from mistakes with memristive synapses T2 - Scientific Reports N2 - AbstractBlooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. This approach provides hardware, local, and energy-efficient learning. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks. KW - RRAM KW - Neural network Y1 - 2024 U6 - https://doi.org/10.1038/s41598-024-57660-4 SN - 2045-2322 VL - 14 IS - 1 ER - TY - CHAP A1 - Wen, Jianan A1 - Vargas, Fabian Luis A1 - Zhu, Fukun A1 - Reiser, Daniel A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Pérez, Eduardo A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Krstic, Milos T1 - Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment T2 - 2024 IEEE 25th Latin American Test Symposium (LATS) N2 - Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1109/LATS62223.2024.10534601 PB - IEEE ER - TY - GEN A1 - Dorai Swamy Reddy, Keerthi A1 - Pérez, Eduardo A1 - Baroni, Andrea A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Marschmeyer, Steffen A1 - Fraschke, Mirko A1 - Lisker, Marco A1 - Wenger, Christian A1 - Mai, Andreas T1 - Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance T2 - The European Physical Journal B N2 - Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1140/epjb/s10051-024-00821-1 SN - 1434-6028 VL - 97 PB - Springer Science and Business Media LLC ER - TY - GEN A1 - Fritscher, Markus A1 - Singh, Simranjeet A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Reiser, Daniel A1 - Mallah, Maen A1 - Hartmann, David A1 - Bende, Ankit A1 - Kempen, Tim A1 - Uhlmann, Max A1 - Kahmen, Gerhard A1 - Fey, Dietmar A1 - Rana, Vikas A1 - Menzel, Stephan A1 - Reichenbach, Marc A1 - Krstic, Milos A1 - Merchant, Farhad A1 - Wenger, Christian T1 - A flexible and fast digital twin for RRAM systems applied for training resilient neural networks T2 - Scientific Reports N2 - Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT). KW - RRAM KW - Neural network KW - digital twin Y1 - 2024 U6 - https://doi.org/10.1038/s41598-024-73439-z SN - 2045-2322 VL - 14 IS - 1 PB - Springer Science and Business Media LLC ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Perez, Eduardo A1 - Uhlmann, Max A1 - Fritscher, Markus A1 - KrishneGowda, Karthik A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator T2 - 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) N2 - The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 % and 18 %, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero. KW - RRAM Y1 - 2024 SN - 978-3-9819263-8-5 SN - 979-8-3503-4860-6 U6 - https://doi.org/10.23919/DATE58400.2024.10546709 SN - 1558-1101 SP - 1 EP - 6 PB - IEEE ER - TY - GEN A1 - Maldonado, David A1 - Baroni, Andrea A1 - Aldana, Samuel A1 - Dorai Swamy Reddy, Keerthi A1 - Pechmann, Stefan A1 - Wenger, Christian A1 - Roldán, Juan Bautista A1 - Pérez, Eduardo T1 - Kinetic Monte Carlo simulation analysis of the conductance drift in Multilevel HfO2-based RRAM devices T2 - Nanoscale N2 - The drift characteristics of valence change memory (VCM) devices have been analyzed through both experimental analysis and 3D kinetic Monte Carlo (kMC) simulations. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1039/d4nr02975e SN - 2040-3364 VL - 16 IS - 40 SP - 19021 EP - 19033 PB - Royal Society of Chemistry (RSC) ER - TY - GEN A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Glukhov, Artem A1 - Bertozzi, Davide A1 - Wenger, Christian A1 - Ielmini, Daniele A1 - Zambelli, Cristian T1 - Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAs T2 - IEEE Transactions on Device and Materials Reliability N2 - Resistive Random Access Memory (RRAM) technology holds promises to improve the Field Programmable Gate Array (FPGA) performance, reduce the area footprint, and dramatically lower run-time energy requirements compared to the state-of-the-art CMOS-based products. However, the integration of RRAM in FPGAs is hindered by the high programming power consumption and by non-ideal behaviors of the device due to its stochastic nature that may overshadow the benefits in normal operation mode. To cope with these challenges, optimized programming strategies have to be investigated. In this work, we explore the impact that different procedures to set the device have on the run-time performance. Process, voltage, and temperature (PVT) variations as well as time-dependent drift effect of the RRAM device are considered in the assessment of 4T1R MUX designs characteristics. The comparison with tradition CMOS implementations reveals how the choice of the target resistive state and the programming algorithm are key design aspects to reduce the run-time delay and energy metrics, while at the same time improving the robustness against the different sources of variations. KW - RRAM KW - FPGA Y1 - 2023 U6 - https://doi.org/10.1109/TDMR.2023.3259015 SN - 1530-4388 VL - 23 IS - 3 SP - 328 EP - 336 ER - TY - GEN A1 - Reiser, Daniel A1 - Reichenbach, Marc A1 - Rizzi, Tommaso A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Wenger, Christian A1 - Zambelli, Cristian A1 - Bertozzi, Davide T1 - Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations T2 - 21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom N2 - In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate multi-level conductance operation. The support of drift models in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they overlook key device- and array-level parameters affecting drift resilience such as the programming algorithm of RRAM cells, the choice of target conductance states and the weight-toconductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability. KW - RRAM Y1 - 2023 SN - 979-8-3503-0024-6 SN - 979-8-3503-0025-3 U6 - https://doi.org/10.1109/NEWCAS57931.2023 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Wen, Jianan A1 - Vargas, Fabian Luis A1 - Zhu, Fukun A1 - Reiser, Daniel A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Perez, Eduardo A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Krstic, Milos T1 - RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation T2 - Microelectronics Reliability N2 - The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current–voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector–matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments. KW - RRAM Y1 - 2025 U6 - https://doi.org/10.1016/j.microrel.2025.115630 SN - 0026-2714 VL - 168 SP - 1 EP - 10 PB - Elsevier BV CY - Amsterdam ER - TY - GEN A1 - Uhlmann, Max A1 - Krysik, Milosz A1 - Wen, Jianan A1 - Frohberg, Max A1 - Baroni, Andrea A1 - Reddy, Keerthi Dorai Swamy A1 - Pérez, Eduardo A1 - Ostrovskyy, Philip A1 - Piotrowski, Krzysztof A1 - Carta, Corrado A1 - Wenger, Christian A1 - Kahmen, Gerhard T1 - A compact one-transistor-multiple-RRAM characterization platform T2 - IEEE transactions on circuits and systems I : regular papers N2 - Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP’s 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 %. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells. KW - RRAM KW - Vector Matrix Multiplication Y1 - 2025 U6 - https://doi.org/10.1109/TCSI.2025.3555234 SN - 1549-8328 SP - 1 EP - 12 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER - TY - GEN A1 - Baroni, Andrea A1 - Pérez, Eduardo A1 - Reddy, Keerthi Dorai Swamy A1 - Pechmann, Stefan A1 - Wenger, Christian A1 - Ielmini, Daniele A1 - Zambelli, Cristian T1 - Enhancing RRAM reliability : exploring the effects of Al doping on HfO2-based devices T2 - IEEE transactions on device and materials reliability N2 - This study provides a comprehensive evaluation of RRAM devices based on HfO2 and Al-doped HfO2 insulators, focusing on critical performance metrics, including Forming yield, Post-Programming Stability (PPS), Fast Drift, Endurance, and Retention at elevated temperatures (125 ∘C). Aluminum doping significantly enhances device reliability and stability, improving Forming yield, reducing current drift during programming and Retention tests, and minimizing variability during Endurance cycling. While Al5%:HfO2 achieves most of the observed benefits compared to pure HfO2, Al7%:HfO2 offers incremental advantages for scenarios requiring extreme reliability. These findings position Al-doped HfO2 devices as a promising solution for RRAM-based systems in memory and neuromorphic computing, highlighting the potential trade-off between performance gains and increased fabrication complexity. This work underlines the importance of material engineering for optimizing RRAM devices in application-specific contexts. KW - RRAM KW - Memristive device Y1 - 2025 U6 - https://doi.org/10.1109/TDMR.2025.3581061 SN - 1530-4388 SN - 1558-2574 SP - 1 EP - 9 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - New York ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Uhlmann, Max A1 - Perez, Eduardo A1 - Wenger, Christian A1 - Krstic, Milos T1 - ReFFT : an energy-efficient RRAM-based FFT accelerator T2 - IEEE transactions on computer-aided design of integrated circuits and systems N2 - The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector–matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks. KW - RRAM KW - Accelerator Y1 - 2025 U6 - https://doi.org/10.1109/TCAD.2025.3627146 SN - 0278-0070 SP - 1 EP - 14 PB - IEEE CY - Piscataway, NJ ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Mistroni, Alberto A1 - Perez, Eduardo A1 - Zambelli, Cristian A1 - Wenger, Christian A1 - Krstic, Milos A1 - Bolzani Pöhls, Leticia Maria T1 - ReDiM : an efficient strategy for read disturb mitigation in RRAM-based accelerators T2 - 2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS) N2 - Resistive RAM (RRAM) has emerged as a promising non-volatile memory technology for implementing energy-efficient hardware accelerators within the in-memory computing (IMC) paradigm. However, due to the immature fabrication process and inherent material instabilities, frequent read operations during computations can induce read disturb effects, leading to unintended resistance drift and potential data corruption. Existing mitigation approaches primarily focus on detecting read disturb effects and triggering memory refresh operations. In this work, we propose an architecture-level solution that mitigates read disturb in RRAM-based accelerators. Our strategy employs crossbar duplication and decomposes the single high input pulse into two lower-amplitude pulses, effectively minimizing the risk of read disturb. To validate our approach, we develop a simulation framework that incorporates measurement data from characterized RRAM devices under read disturb stress conditions. Experimental results on VGG-8 with CIFAR-10 demonstrate that the proposed method significantly mitigates inference accuracy degradation caused by read disturb in RRAM-based accelerators, while incurring modest area and energy overheads of 12.32% and 2.15%, respectively. This work provides a practical and scalable solution for enhancing the robustness of RRAM-based accelerators in edge and high-performance computing applications. KW - RRAM KW - Resistive RAM KW - In-memory Computing KW - AI Accelerator KW - Read Disturb KW - Reliability Y1 - 2025 SN - 979-8-3315-3334-2 U6 - https://doi.org/10.1109/IOLTS65288.2025.11117065 SP - 1 EP - 7 PB - IEEE CY - Piscataway, NJ ER -