TY - GEN A1 - Baroni, Andrea A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Pérez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - Tackling the Low Conductance State Drift through Incremental Reset and Verify in RRAM Arrays T2 - 2021 IEEE International Integrated Reliability Workshop (IIRW), South Lake Tahoe, CA, USA, 10 December 2021 N2 - Resistive switching memory (RRAM) is a promising technology for highly efficient computing scenarios. RRAM arrays enabled the acceleration of neural networks for artificial intelligence and the creation of In-Memory Computing circuits. However, the arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation in those applications. Among those, one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are fundamental for an accurate Multi-level conductance operation. In this work, we tackle the issue by developing an Incremental Reset and Verify technique showing enhanced variability and reliability features compared with a traditional refresh-based approach. KW - RRAM KW - resistive switching KW - neural network Y1 - 2021 SN - 978-1-6654-1794-5 SN - 978-1-6654-1795-2 U6 - https://doi.org/10.1109/IIRW53245.2021.9635613 SN - 2374-8036 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Mannocci, Piergiulio A1 - Baroni, Andrea A1 - Melacarne, Enrico A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Pérez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - In-Memory Principal Component Analysis by Crosspoint Array of Rresistive Switching Memory T2 - IEEE Nanotechnology Magazine N2 - In Memory Computing (IMC) is one of the most promising candidates for data-intensive computing accelerators of machine learning (ML). A key ML algorithm for dimensionality reduction and classification is principal component analysis (PCA), which heavily relies on matrixvector multiplications (MVM) for which classic von Neumann architectures are not optimized. Here, we provide the experimental demonstration of a new IMCbased PCA algorithm based on power iteration and deflation executed in a 4-kbit array of resistive switching random-access memory (RRAM). The classification accuracy of the Wisconsin Breast Cancer data set reaches 95.43%, close to floatingpoint implementation. Our simulations indicate a 250× improvement in energy efficiency compared to commercial GPUs, thus supporting IMC for energy-efficient ML in modern data-intensive computing. KW - RRAM KW - Multilevel switching KW - neural network Y1 - 2022 U6 - https://doi.org/10.1109/MNANO.2022.3141515 SN - 1932-4510 VL - 16 IS - 2 SP - 4 EP - 13 ER - TY - GEN A1 - Glukhov, Artem A1 - Milo, Valerio A1 - Baroni, Andrea A1 - Lepri, Nicola A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Pérez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators T2 - 2022 IEEE International Reliability Physics Symposium (IRPS) N2 - Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators. KW - RRAM KW - Multilevel switching KW - neural network Y1 - 2022 SN - 978-1-6654-7950-9 SN - 978-1-6654-7951-6 U6 - https://doi.org/10.1109/IRPS48227.2022.9764497 SN - 2473-2001 SP - 3C.3-1 EP - 3C.3-7 PB - Institute of Electrical and Electronics Engineers (IEEE) ER - TY - GEN A1 - Baroni, Andrea A1 - Glukhov, Artem A1 - Pérez, Eduardo A1 - Wenger, Christian A1 - Calore, Enrico A1 - Schifano, Sebastiano Fabio A1 - Olivo, Piero A1 - Ielmini, Daniele A1 - Zambelli, Cristian T1 - An energy-efficient in-memory computing architecture for survival data analysis based on resistive switching memories T2 - Frontiers in Neuroscience N2 - One of the objectives fostered in medical science is the so-called precision medicine, which requires the analysis of a large amount of survival data from patients to deeply understand treatment options. Tools like Machine Learning and Deep Neural Networks are becoming a de-facto standard. Nowadays, computing facilities based on the Von Neumann architecture are devoted to these tasks, yet rapidly hitting a bottleneck in performance and energy efficiency. The In-Memory Computing (IMC) architecture emerged as a revolutionary approach to overcome that issue. In this work, we propose an IMC architecture based on Resistive switching memory (RRAM) crossbar arrays to provide a convenient primitive for matrix–vector multiplication in a single computational step. This opens massive performance improvement in the acceleration of a neural network that is frequently used in survival analysis of biomedical records, namely the DeepSurv. We explored how the synaptic weights mapping strategy and the programming algorithms developed to counter RRAM non-idealities expose a performance/energy trade-off. Finally, we assessed the benefits of the proposed architectures with respect to a GPU-based realization of the same task, evidencing a tenfold improvement in terms of performance and three orders of magnitude with respect to energy efficiency. KW - RRAM KW - In-Memory Computing KW - Multilevel switching Y1 - 2022 U6 - https://doi.org/10.3389/fnins.2022.932270 SN - 1662-4548 VL - Vol. 16 SP - 1 EP - 16 ER - TY - GEN A1 - Baroni, Andrea A1 - Glukhov, Artem A1 - Pérez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele A1 - Olivo, Piero A1 - Zambelli, Cristian T1 - Low Conductance State Drift Characterization and Mitigation in Resistive Switching Memories (RRAM) for Artificial Neural Networks T2 - IEEE Transactions on Device and Materials Reliability N2 - The crossbar structure of Resistive-switching random access memory (RRAM) arrays enabled the In-Memory Computing circuits paradigm, since they imply the native acceleration of a crucial operations in this scenario, namely the Matrix-Vector-Multiplication (MVM). However, RRAM arrays are affected by several issues materializing in conductance variations that might cause severe performance degradation. A critical one is related to the drift of the low conductance states appearing immediately at the end of program and verify algorithms that are mandatory for an accurate multi-level conductance operation. In this work, we analyze the benefits of a new programming algorithm that embodies Set and Reset switching operations to achieve better conductance control and lower variability. Data retention analysis performed with different temperatures for 168 hours evidence its superior performance with respect to standard programming approach. Finally, we explored the benefits of using our methodology at a higher abstraction level, through the simulation of an Artificial Neural Network for image recognition task (MNIST dataset). The accuracy achieved shows higher performance stability over temperature and time. KW - RRAM KW - neural network KW - Multilevel switching Y1 - 2022 U6 - https://doi.org/10.1109/TDMR.2022.3182133 SN - 1530-4388 VL - 22 IS - 3 SP - 340 EP - 347 ER - TY - GEN A1 - Glukhov, Artem A1 - Lepri, Nicola A1 - Milo, Valerio A1 - Baroni, Andrea A1 - Zambelli, Cristian A1 - Olivo, Piero A1 - Pérez, Eduardo A1 - Wenger, Christian A1 - Ielmini, Daniele T1 - End-to-end modeling of variability-aware neural networks based on resistive-switching memory arrays T2 - Proc. 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2022) N2 - Resistive-switching random access memory (RRAM) is a promising technology that enables advanced applications in the field of in-memory computing (IMC). By operating the memory array in the analogue domain, RRAM-based IMC architectures can dramatically improve the energy efficiency of deep neural networks (DNNs). However, achieving a high inference accuracy is challenged by significant variation of RRAM conductance levels, which can be compensated by (i) advanced programming techniques and (ii) variability-aware training (VAT) algorithms. In both cases, however, detailed knowledge and accurate physics-based statistical models of RRAM are needed to develop programming and VAT methodologies. This work presents an end-to-end approach to the development of highly-accurate IMC circuits with RRAM, encompassing the device modeling, the precise programming algorithm, and the VAT simulations to maximize the DNN classification accuracy in presence of conductance variations. KW - RRAM KW - HfO2 KW - neural network KW - memristive switching Y1 - 2022 U6 - https://doi.org/10.1109/VLSI-SoC54400.2022.9939653 SP - 1 EP - 5 ER - TY - GEN A1 - Wen, Jianan A1 - Baroni, Andrea A1 - Pérez, Eduardo A1 - Ulbricht, Markus A1 - Wenger, Christian A1 - Krstic, Milos T1 - Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages T2 - 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) N2 - RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states. KW - RRAM KW - Multilevel switching KW - AI accelarator Y1 - 2022 SN - 978-1-6654-5938-9 SN - 978-1-6654-5937-2 U6 - https://doi.org/10.1109/DFT56152.2022.9962345 SN - 2765-933X SP - 1 EP - 6 ER - TY - GEN A1 - Nikiruy, Kristina A1 - Pérez, Eduardo A1 - Baroni, Andrea A1 - Dorai Swamy Reddy, Keerthi A1 - Pechmann, Stefan A1 - Wenger, Christian A1 - Ziegler, Martin T1 - Blooming and pruning: learning from mistakes with memristive synapses T2 - Scientific Reports N2 - AbstractBlooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. This approach provides hardware, local, and energy-efficient learning. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks. KW - RRAM KW - Neural network Y1 - 2024 U6 - https://doi.org/10.1038/s41598-024-57660-4 SN - 2045-2322 VL - 14 IS - 1 ER - TY - CHAP A1 - Wen, Jianan A1 - Vargas, Fabian Luis A1 - Zhu, Fukun A1 - Reiser, Daniel A1 - Baroni, Andrea A1 - Fritscher, Markus A1 - Pérez, Eduardo A1 - Reichenbach, Marc A1 - Wenger, Christian A1 - Krstic, Milos T1 - Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment T2 - 2024 IEEE 25th Latin American Test Symposium (LATS) N2 - Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1109/LATS62223.2024.10534601 PB - IEEE ER - TY - GEN A1 - Dorai Swamy Reddy, Keerthi A1 - Pérez, Eduardo A1 - Baroni, Andrea A1 - Mahadevaiah, Mamathamba Kalishettyhalli A1 - Marschmeyer, Steffen A1 - Fraschke, Mirko A1 - Lisker, Marco A1 - Wenger, Christian A1 - Mai, Andreas T1 - Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance T2 - The European Physical Journal B N2 - Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2 dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO2 dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology. KW - RRAM Y1 - 2024 U6 - https://doi.org/10.1140/epjb/s10051-024-00821-1 SN - 1434-6028 VL - 97 PB - Springer Science and Business Media LLC ER -