TY - GEN A1 - Azad, Siavoosh Payandeh A1 - Niazmand, Behrad A1 - Janson, Karl A1 - George, Nevin A1 - Oyeniran, Stephen Adeboye A1 - Putkaradze, Tsotne A1 - Kaur, Apneet A1 - Raik, Jaan A1 - Jervan, Gert A1 - Ubar, Raimund A1 - Hollstein, Thomas T1 - From online fault detection to fault management in Network-on-Chips: A ground-up approach T2 - IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Dresden, Germany, 19-21 April 2017 Y1 - 2017 SN - 978-1-5386-0472-4 SN - 978-1-5386-0473-1 U6 - https://doi.org/10.1109/DDECS.2017.7934565 SN - 2473-2117 ER - TY - GEN A1 - George, Nevin A1 - Hübner, Michael A1 - Vierhaus, Heinrich Theodor T1 - From Fault Tolerance to Error Resilience: Co-Designing for Self-Awareness T2 - Proc. PhD Forum of the 9th BELAS Summer School, IHP, Frankfurt/Oder Y1 - 2019 UR - https://www.google.de/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact=8&ved=2ahUKEwjs5unQ-MvoAhWSUBUIHWVeBFIQFjABegQIAxAB&url=https%3A%2F%2Fwww.ihp-microelectronics.com%2Fdownloads%2F3616%2FBELAS19_paper_17.pdf&usg=AOvVaw2Na-b6H-YWFoZRCLRWzzYs ER - TY - GEN A1 - Hoffmann, Javier Eduardo A1 - Mahmood, Safdar A1 - Suawa Fogou, Priscile A1 - George, Nevin A1 - Raha, Solaiman A1 - Safi, Sabur A1 - Schmailzl, Kurt JG A1 - Brandalero, Marcelo A1 - Hübner, Michael T1 - A Survey on Machine Learning Approaches to ECG Processing T2 - 2020 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA), 23-25 Sept. 2020 , Poznan, Poland Y1 - 2020 UR - https://ieeexplore.ieee.org/document/9241283 SN - 978-83-62065-39-4 SN - 978-83-62065-37-0 SN - 978-1-7281-7746-5 ER - TY - GEN A1 - Segabinazzi Ferreira, Raphael A1 - George, Nevin A1 - Chen, Junchao A1 - Hübner, Michael A1 - Krstic, Milos A1 - Nolte, Jörg A1 - Vierhaus, Heinrich Theodor T1 - Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness T2 - Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design N2 - Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on- line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system. Y1 - 2019 SN - 978-3-902457-54-7 U6 - https://doi.org/10.26127/BTUOpen-5050 PB - SEA-Publications CY - Kallithea, Chalkidiki (Greece) ER - TY - GEN A1 - Segabinazzi Ferreira, Raphael A1 - Nolte, Jörg A1 - Vargas, Fabian A1 - George, Nevin A1 - Hübner, Michael T1 - Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications T2 - IEEE Latin American Test Symposium (LATS), Maceió, Brazil Y1 - 2020 U6 - https://doi.org/10.1109/LATS49555.2020.9093692 ER -