<?xml version="1.0" encoding="utf-8"?>
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  <doc>
    <id>22547</id>
    <completedYear/>
    <publishedYear>2018</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber>6</pageNumber>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject</type>
    <publisherName>IEEE</publisherName>
    <publisherPlace>Piscataway, NJ</publisherPlace>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2018-11-12</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Impact of Resistive Open and Bridge Defects on the SET Robustness of CMOS Combinational Logic</title>
    <parentTitle language="eng">IEEE East-West Design &amp; Test Symposium (EWDTS 2018), Kazan, Russia, 14 - 17 September 2018</parentTitle>
    <identifier type="isbn">978-1-5386-5709-6</identifier>
    <identifier type="doi">10.1109/EWDTS.2018.8524748</identifier>
    <enrichment key="BTU">an der BTU erstellt / created at BTU</enrichment>
    <author>
      <firstName>Marko</firstName>
      <lastName>Andjelkovic</lastName>
    </author>
    <submitter>
      <firstName>Heike</firstName>
      <lastName>Wasgien</lastName>
    </submitter>
    <author>
      <firstName>Zoran</firstName>
      <lastName>Stamenković</lastName>
    </author>
    <author>
      <firstName>Milos</firstName>
      <lastName>Krstic</lastName>
    </author>
    <author>
      <firstName>Rolf</firstName>
      <lastName>Kraemer</lastName>
    </author>
    <collection role="institutes" number="1222">FG Systeme</collection>
  </doc>
</export-example>
