<?xml version="1.0" encoding="utf-8"?>
<export-example>
  <doc>
    <id>34329</id>
    <completedYear/>
    <publishedYear>2024</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber>13</pageNumber>
    <edition/>
    <issue>1</issue>
    <volume>14</volume>
    <type>articler</type>
    <publisherName>Springer Science and Business Media LLC</publisherName>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2024-10-29</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">A flexible and fast digital twin for RRAM systems applied for training resilient neural networks</title>
    <abstract language="eng">Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).</abstract>
    <parentTitle language="eng">Scientific Reports</parentTitle>
    <identifier type="doi">10.1038/s41598-024-73439-z</identifier>
    <identifier type="issn">2045-2322</identifier>
    <enrichment key="opus_doi_flag">true</enrichment>
    <enrichment key="opus_doi_json">{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,11]],"date-time":"2024-10-11T04:14:12Z","timestamp":1728620052786},"reference-count":38,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2024,10,10]],"date-time":"2024-10-10T00:00:00Z","timestamp":1728518400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0"},{"start":{"date-parts":[[2024,10,10]],"date-time":"2024-10-10T00:00:00Z","timestamp":1728518400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","award":["441921944","422738993"],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002347","name":"Bundesministerium f\u00fcr Bildung und Forschung","doi-asserted-by":"publisher","award":["16ES1128K","16KISK026","16ME0386","16ME0398K"],"id":[{"id":"10.13039\/501100002347","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002347","name":"Bundesministerium f\u00fcr Bildung und Forschung","doi-asserted-by":"publisher","award":["16ME0399"],"id":[{"id":"10.13039\/501100002347","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Sci Rep"],"DOI":"10.1038\/s41598-024-73439-z","type":"journal-article","created":{"date-parts":[[2024,10,10]],"date-time":"2024-10-10T08:02:15Z","timestamp":1728547335000},"update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A flexible and fast digital twin for RRAM systems applied for training resilient neural networks"],"prefix":"10.1038","volume":"14","author":[{"given":"Markus","family":"Fritscher","sequence":"first","affiliation":[]},{"given":"Simranjeet","family":"Singh","sequence":"additional","affiliation":[]},{"given":"Tommaso","family":"Rizzi","sequence":"additional","affiliation":[]},{"given":"Andrea","family":"Baroni","sequence":"additional","affiliation":[]},{"given":"Daniel","family":"Reiser","sequence":"additional","affiliation":[]},{"given":"Maen","family":"Mallah","sequence":"additional","affiliation":[]},{"given":"David","family":"Hartmann","sequence":"additional","affiliation":[]},{"given":"Ankit","family":"Bende","sequence":"additional","affiliation":[]},{"given":"Tim","family":"Kempen","sequence":"additional","affiliation":[]},{"given":"Max","family":"Uhlmann","sequence":"additional","affiliation":[]},{"given":"Gerhard","family":"Kahmen","sequence":"additional","affiliation":[]},{"given":"Dietmar","family":"Fey","sequence":"additional","affiliation":[]},{"given":"Vikas","family":"Rana","sequence":"additional","affiliation":[]},{"given":"Stephan","family":"Menzel","sequence":"additional","affiliation":[]},{"given":"Marc","family":"Reichenbach","sequence":"additional","affiliation":[]},{"given":"Milos","family":"Krstic","sequence":"additional","affiliation":[]},{"given":"Farhad","family":"Merchant","sequence":"additional","affiliation":[]},{"given":"Christian","family":"Wenger","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2024,10,10]]},"reference":[{"key":"73439_CR1","doi-asserted-by":"publisher","first-page":"1700561","DOI":"10.1002\/aelm.201700561","volume":"4","author":"W Banerjee","year":"2018","unstructured":"Banerjee, W. et al. Design of CMOS compatible, high-speed, highly-stable complementary switching with multilevel operation in 3D vertically stacked novel HfO2\/Al2O3\/TiOx (HAT) RRAM. Adv. Electron. Mater. 4, 1700561 (2018).","journal-title":"Adv. Electron. Mater."},{"key":"73439_CR2","doi-asserted-by":"crossref","unstructured":"Fritscher, M. et al. Simulating large neural networks embedding MLC RRAM as weight storage considering device variations. In 2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS), 1\u20134 (IEEE, 2021).","DOI":"10.1109\/LASCAS51355.2021.9459159"},{"key":"73439_CR3","doi-asserted-by":"crossref","unstructured":"Fritscher, M. et al. Prototyping reconfigurable RRAM-based AI accelerators using the RISC-V ecosystem and digital twins. In International Conference on High Performance Computing, 500\u2013514 (Springer, 2023).","DOI":"10.1007\/978-3-031-40843-4_37"},{"key":"73439_CR4","doi-asserted-by":"publisher","first-page":"4397","DOI":"10.1109\/TED.2021.3097975","volume":"68","author":"BQ Le","year":"2021","unstructured":"Le, B. Q. et al. Radar: A fast and energy-efficient programming technique for multiple bits-per-cell RRAM arrays. IEEE Trans. Electron Devices 68, 4397\u20134403 (2021).","journal-title":"IEEE Trans. Electron Devices"},{"key":"73439_CR5","doi-asserted-by":"publisher","first-page":"64","DOI":"10.1109\/JEDS.2016.2618425","volume":"5","author":"GA P\u00e9rez","year":"2016","unstructured":"P\u00e9rez, G. A., Zambelli, C., Olivo, P. &amp; Wenger, C. Impact of the incremental programming algorithm on the filament conduction in HfO2-based RRAM arrays. IEEE J. Electron Devices Soc. 5, 64\u201368 (2016).","journal-title":"IEEE J. Electron Devices Soc."},{"key":"73439_CR6","doi-asserted-by":"crossref","unstructured":"Zahid, U., Gambardella, G., Fraser, N.\u00a0J., Blott, M. &amp; Vissers, K. Fat: Training neural networks for reliable inference under hardware faults. In 2020 IEEE Int. Test Conf. (ITC), 1\u201310 (IEEE, 2020).","DOI":"10.1109\/ITC44778.2020.9325249"},{"key":"73439_CR7","doi-asserted-by":"publisher","first-page":"2306","DOI":"10.1109\/TCAD.2020.3043731","volume":"40","author":"X Peng","year":"2020","unstructured":"Peng, X., Huang, S., Jiang, H., Lu, A. &amp; Yu, S. DNN+ NeuroSim V2. 0: An end-to-end benchmarking framework for compute-in-memory accelerators for on-chip training. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 40, 2306\u20132319 (2020).","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"73439_CR8","doi-asserted-by":"publisher","first-page":"1121","DOI":"10.1007\/s10825-017-1101-9","volume":"16","author":"D Ielmini","year":"2017","unstructured":"Ielmini, D. &amp; Milo, V. Physics-based modeling approaches of resistive switching devices for memory and in-memory computing applications. J. Comp. Electron. 16, 1121\u20131143 (2017).","journal-title":"J. Comp. Electron."},{"key":"73439_CR9","doi-asserted-by":"publisher","first-page":"505","DOI":"10.1109\/TNANO.2015.2411774","volume":"14","author":"S Tappertzhofen","year":"2015","unstructured":"Tappertzhofen, S. et al. Modeling of quantized conductance effects in electrochemical metallization cells. IEEE Trans. Nanotechnol. 14, 505\u2013512 (2015).","journal-title":"IEEE Trans. Nanotechnol."},{"key":"73439_CR10","doi-asserted-by":"publisher","first-page":"1884","DOI":"10.1109\/TED.2016.2545412","volume":"63","author":"Z Jiang","year":"2016","unstructured":"Jiang, Z. et al. A compact model for metal-oxide resistive random access memory with experiment verification. IEEE Trans. Electron. Devices 63, 1884\u20131892 (2016).","journal-title":"IEEE Trans. Electron. Devices"},{"key":"73439_CR11","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1186\/s11671-017-2419-8","volume":"13","author":"D Panda","year":"2018","unstructured":"Panda, D., Sahu, P. P. &amp; Tseng, T. Y. A collective study on modeling and simulation of resistive random access memory. Nanoscale Res. Lett. 13, 1\u201348 (2018).","journal-title":"Nanoscale Res. Lett."},{"key":"73439_CR12","doi-asserted-by":"publisher","first-page":"994","DOI":"10.1109\/TCAD.2012.2185930","volume":"31","author":"X Dong","year":"2012","unstructured":"Dong, X., Xu, C., Xie, Y. &amp; Jouppi, N. P. Nvsim: a circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31, 994\u20131007\u00a0(2012).","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"73439_CR13","first-page":"28","volume":"27","author":"N Muralimanohar","year":"2009","unstructured":"Muralimanohar, N., Balasubramonian, R. &amp; Jouppi, N. P. Cacti 6.0: A tool to model large caches. HP Lab. 27, 28 (2009).","journal-title":"HP Lab."},{"key":"73439_CR14","doi-asserted-by":"crossref","unstructured":"Peng, X., Huang, S., Luo, Y., Sun, X. &amp; Yu, S. DNN + Neurosim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies. In 2019 IEEE International Electron Devices Meeting (IEDM), 32\u20135 (IEEE, 2019).","DOI":"10.1109\/IEDM19573.2019.8993491"},{"key":"73439_CR15","doi-asserted-by":"publisher","first-page":"3067","DOI":"10.1109\/TCAD.2018.2789723","volume":"37","author":"P-Y Chen","year":"2018","unstructured":"Chen, P.-Y., Peng, X. &amp; Yu, S. Neurosim: A circuit-level macro model for benchmarking neuro-inspired architectures in online learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37, 3067\u20133080 (2018).","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"73439_CR16","unstructured":"Paszke, A. et al. Pytorch: An imperative style, high-performance deep learning library. In Advances in Neural Information Processing Systems Vol. 32, 8024\u20138035 (Curran Associates, Inc., 2019)."},{"key":"73439_CR17","doi-asserted-by":"crossref","unstructured":"Zhu, Z. et al. Mnsim 2.0: A behavior-level modeling tool for memristor-based neuromorphic computing systems. In Proceedings of the 2020 on Great Lakes Symposium on VLSI, 83\u201388 (2020).","DOI":"10.1145\/3386263.3407647"},{"key":"73439_CR18","doi-asserted-by":"crossref","unstructured":"Lin, M.-Y. et al. Dl-rsim: A simulation framework to enable reliable reram-based accelerators for deep learning. In 2018 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), 1\u20138 (2018).","DOI":"10.1145\/3240765.3240800"},{"key":"73439_CR19","doi-asserted-by":"publisher","first-page":"124","DOI":"10.1016\/j.neucom.2022.02.043","volume":"485","author":"C Lammie","year":"2022","unstructured":"Lammie, C., Xiang, W., Linares-Barranco, B. &amp; Azghadi, M. R. Memtorch: An open-source simulation framework for memristive deep learning systems. Neurocomputing 485, 124\u2013133 (2022).","journal-title":"Neurocomputing"},{"key":"73439_CR20","first-page":"786","volume":"62","author":"S Kvatinsky","year":"2015","unstructured":"Kvatinsky, S., Ramadan, M., Friedman, E. G. &amp; Kolodny, A. Vteam: A general model for voltage-controlled memristors. IEEE Trans. Circuits Syst. II Express Briefs 62, 786\u2013790 (2015).","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"73439_CR21","doi-asserted-by":"publisher","first-page":"3151","DOI":"10.1109\/TCAD.2018.2791468","volume":"37","author":"I Messaris","year":"2018","unstructured":"Messaris, I. et al. A data-driven verilog-a reram model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37, 3151\u20133162 (2018).","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"73439_CR22","doi-asserted-by":"crossref","unstructured":"Waterman, A. et al. The risc-v instruction set manual. Volume I: User-Level ISA, version 2, 1\u201379 (2014).","DOI":"10.21236\/ADA605735"},{"key":"73439_CR23","doi-asserted-by":"crossref","unstructured":"Gaba, S., Knag, P., Zhang, Z. &amp; Lu, W. Memristive devices for stochastic computing. In 2014 IEEE Int. Symp. on Circuits and Systems (ISCAS), 2592\u20132595 (IEEE, 2014).","DOI":"10.1109\/ISCAS.2014.6865703"},{"key":"73439_CR24","doi-asserted-by":"publisher","first-page":"104","DOI":"10.1016\/j.mee.2019.05.004","volume":"214","author":"E P\u00e9rez","year":"2019","unstructured":"P\u00e9rez, E. et al. Analysis of the statistics of device-to-device and cycle-to-cycle variability in tin\/Ti\/Al: HfO2\/tin RRAMS. Microelectron. Eng. 214, 104\u2013109 (2019).","journal-title":"Microelectron. Eng."},{"key":"73439_CR25","doi-asserted-by":"crossref","unstructured":"Milo, V. et al. Multilevel hfo2-based rram devices for low-power neuromorphic networks. APL Mater. 7 (2019).","DOI":"10.1063\/1.5108650"},{"key":"73439_CR26","doi-asserted-by":"crossref","unstructured":"Bende, A. et al. Experimental validation of memristor-aided logic using 1t1r tao x rram crossbar array. In 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), 565\u2013570 (IEEE, 2024).","DOI":"10.1109\/VLSID60093.2024.00100"},{"key":"73439_CR27","doi-asserted-by":"crossref","unstructured":"Wu, L. et al. Study on high-resistance state instability of TaOx-based RRAM. In 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 1\u20133 (2018).","DOI":"10.1109\/ICSICT.2018.8565770"},{"key":"73439_CR28","doi-asserted-by":"publisher","first-page":"32","DOI":"10.1109\/LED.2016.2630044","volume":"38","author":"X Li","year":"2017","unstructured":"Li, X., Wu, H., Gao, B., Deng, N. &amp; Qian, H. Short time high-resistance state instability of TaOx-based RRAM devices. IEEE Electron Device Lett. 38, 32\u201335 (2017).","journal-title":"IEEE Electron Device Lett."},{"key":"73439_CR29","unstructured":"Sobel, I. An isotropic 3x3 image gradient operator. Presentation at Stanford A.I. Project 1968 (2014)."},{"key":"73439_CR30","doi-asserted-by":"publisher","first-page":"1368","DOI":"10.1166\/jmihi.2018.2442","volume":"8","author":"F Liu","year":"2018","unstructured":"Liu, F. et al. An open access database for evaluating the algorithms of electrocardiogram rhythm and morphology abnormality detection. J. Med. Imaging Health Inform. 8, 1368\u20131373 (2018).","journal-title":"J. Med. Imaging Health Inform."},{"key":"73439_CR31","doi-asserted-by":"publisher","first-page":"2693","DOI":"10.1109\/TED.2021.3072868","volume":"68","author":"E Perez","year":"2021","unstructured":"Perez, E., Mahadevaiah, M. K., Quesada, E.P.-B. &amp; Wenger, C. Variability and energy consumption tradeoffs in multilevel programming of RRAM arrays. IEEE Trans. Electron Devices 68, 2693\u20132698 (2021).","journal-title":"IEEE Trans. Electron Devices"},{"key":"73439_CR32","doi-asserted-by":"crossref","unstructured":"Kempen, T., Waser, R. &amp; Rana, V. 50x endurance improvement in TaOx RRAM by extrinsic doping. In IEEE Int. Memory Workshop (IMW), 1\u20134 (2021).","DOI":"10.1109\/IMW51353.2021.9439591"},{"key":"73439_CR33","unstructured":"NVIDIA. H100 datasheet. https:\/\/www.nvidia.com\/en-us\/data-center\/h100\/ (2023)."},{"key":"73439_CR34","unstructured":"AMD. High performance computing (hpc) tuning guide for amd epyc 9004 series processors. https:\/\/www.amd.com\/ (2024)."},{"key":"73439_CR35","doi-asserted-by":"publisher","first-page":"427","DOI":"10.1002\/(SICI)1097-024X(199604)26:4&lt;427::AID-SPE20&gt;3.0.CO;2-H","volume":"26","author":"G Graefe","year":"1996","unstructured":"Graefe, G. Iterators, schedulers, and distributed-memory parallelism. Softw. Pract. Exp. 26, 427\u2013452 (1996).","journal-title":"Softw. Pract. Exp."},{"key":"73439_CR36","doi-asserted-by":"publisher","first-page":"377","DOI":"10.1017\/S0956796809007291","volume":"19","author":"J Gibbons","year":"2009","unstructured":"Gibbons, J. &amp; Oliveira, B. C. D. S. The essence of the iterator pattern. J. Funct. Program. 19, 377\u2013402 (2009).","journal-title":"J. Funct. Program."},{"key":"73439_CR37","doi-asserted-by":"publisher","first-page":"3408","DOI":"10.1021\/acs.jcim.0c00451","volume":"60","author":"X Gao","year":"2020","unstructured":"Gao, X., Ramezanghorbani, F., Isayev, O., Smith, J. S. &amp; Roitberg, A. E. TorchANI: a free and open source PyTorch-based deep learning implementation of the ANI neural network potentials. J. Chem. Inf. Model. 60, 3408\u20133415 (2020).","journal-title":"J. Chem. Inf. Model."},{"key":"73439_CR38","unstructured":"Yin, P. et al. Understanding straight-through estimator in training activation quantized neural nets. arXiv preprint arXiv:1903.05662 (2019)."}],"container-title":["Scientific Reports"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.nature.com\/articles\/s41598-024-73439-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/www.nature.com\/articles\/s41598-024-73439-z","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/www.nature.com\/articles\/s41598-024-73439-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,10]],"date-time":"2024-10-10T08:04:33Z","timestamp":1728547473000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.nature.com\/articles\/s41598-024-73439-z"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,10]]},"references-count":38,"journal-issue":{"issue":"1","published-online":{"date-parts":[[2024,12]]}},"alternative-id":["73439"],"URL":"http:\/\/dx.doi.org\/10.1038\/s41598-024-73439-z","relation":{},"ISSN":["2045-2322"],"issn-type":[{"value":"2045-2322","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,10,10]]},"assertion":[{"value":"9 May 2024","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"16 September 2024","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"10 October 2024","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare no competing interests.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Competing interests"}}],"article-number":"23695"}}</enrichment>
    <enrichment key="opus_crossrefDocumentType">journal-article</enrichment>
    <enrichment key="opus_crossrefLicence">https://creativecommons.org/licenses/by-nc-nd/4.0</enrichment>
    <enrichment key="opus_import_origin">crossref</enrichment>
    <enrichment key="opus_doiImportPopulated">PersonAuthorFirstName_1,PersonAuthorLastName_1,PersonAuthorFirstName_2,PersonAuthorLastName_2,PersonAuthorFirstName_3,PersonAuthorLastName_3,PersonAuthorFirstName_4,PersonAuthorLastName_4,PersonAuthorFirstName_5,PersonAuthorLastName_5,PersonAuthorFirstName_6,PersonAuthorLastName_6,PersonAuthorFirstName_7,PersonAuthorLastName_7,PersonAuthorFirstName_8,PersonAuthorLastName_8,PersonAuthorFirstName_9,PersonAuthorLastName_9,PersonAuthorFirstName_10,PersonAuthorLastName_10,PersonAuthorFirstName_11,PersonAuthorLastName_11,PersonAuthorFirstName_12,PersonAuthorLastName_12,PersonAuthorFirstName_13,PersonAuthorLastName_13,PersonAuthorFirstName_14,PersonAuthorLastName_14,PersonAuthorFirstName_15,PersonAuthorLastName_15,PersonAuthorFirstName_16,PersonAuthorLastName_16,PersonAuthorFirstName_17,PersonAuthorLastName_17,PersonAuthorFirstName_18,PersonAuthorLastName_18,PublisherName,TitleMain_1,Language,TitleParent_1,ArticleNumber,Issue,Volume,PublishedYear,IdentifierIssn,Enrichmentopus_crossrefLicence</enrichment>
    <enrichment key="BTU">an der BTU erstellt / created at BTU</enrichment>
    <enrichment key="Referiert">Beitrag ist referiert / Article peer-reviewed</enrichment>
    <enrichment key="Publikationsweg">Open Access</enrichment>
    <enrichment key="opus.source">doi-import</enrichment>
    <enrichment key="Fprofil">4 Künstliche Intelligenz und Sensorik / Artificial Intelligence and Sensor Technology</enrichment>
    <author>
      <firstName>Markus</firstName>
      <lastName>Fritscher</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Simranjeet</firstName>
      <lastName>Singh</lastName>
    </author>
    <author>
      <firstName>Tommaso</firstName>
      <lastName>Rizzi</lastName>
    </author>
    <author>
      <firstName>Andrea</firstName>
      <lastName>Baroni</lastName>
    </author>
    <author>
      <firstName>Daniel</firstName>
      <lastName>Reiser</lastName>
    </author>
    <author>
      <firstName>Maen</firstName>
      <lastName>Mallah</lastName>
    </author>
    <author>
      <firstName>David</firstName>
      <lastName>Hartmann</lastName>
    </author>
    <author>
      <firstName>Ankit</firstName>
      <lastName>Bende</lastName>
    </author>
    <author>
      <firstName>Tim</firstName>
      <lastName>Kempen</lastName>
    </author>
    <author>
      <firstName>Max</firstName>
      <lastName>Uhlmann</lastName>
    </author>
    <author>
      <firstName>Gerhard</firstName>
      <lastName>Kahmen</lastName>
    </author>
    <author>
      <firstName>Dietmar</firstName>
      <lastName>Fey</lastName>
    </author>
    <author>
      <firstName>Vikas</firstName>
      <lastName>Rana</lastName>
    </author>
    <author>
      <firstName>Stephan</firstName>
      <lastName>Menzel</lastName>
    </author>
    <author>
      <firstName>Marc</firstName>
      <lastName>Reichenbach</lastName>
    </author>
    <author>
      <firstName>Milos</firstName>
      <lastName>Krstic</lastName>
    </author>
    <author>
      <firstName>Farhad</firstName>
      <lastName>Merchant</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Neural network</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>digital twin</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
  </doc>
  <doc>
    <id>34340</id>
    <completedYear/>
    <publishedYear>2023</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>1</pageFirst>
    <pageLast>6</pageLast>
    <pageNumber>6</pageNumber>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject_ref</type>
    <publisherName>ACM</publisherName>
    <publisherPlace>New York, NY, USA</publisherPlace>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2024-10-29</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">LUT-based RRAM model for neural accelerator circuit simulation</title>
    <abstract language="eng">Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices’ models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP’s 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis.</abstract>
    <parentTitle language="eng">Proceedings of the 18th ACM International Symposium on Nanoscale Architectures</parentTitle>
    <identifier type="doi">10.1145/3611315.3633273</identifier>
    <enrichment key="opus_doi_flag">true</enrichment>
    <enrichment key="opus_doi_json">{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T02:40:55Z","timestamp":1725763255996},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","funder":[{"name":"Deutsche Forschungsgemeinschaft (DFG)","award":["434434223 ? SFB 1461 and 441921944"]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,12,18]]},"DOI":"10.1145\/3611315.3633273","type":"proceedings-article","created":{"date-parts":[[2024,1,25]],"date-time":"2024-01-25T18:09:34Z","timestamp":1706206174000},"page":"1-6","update-policy":"http:\/\/dx.doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["LUT-based RRAM Model for Neural Accelerator Circuit Simulation"],"prefix":"10.1145","author":[{"ORCID":"http:\/\/orcid.org\/0009-0002-8625-2040","authenticated-orcid":false,"given":"Max","family":"Uhlmann","sequence":"first","affiliation":[{"name":"IHP - Leibniz Institut fuer innovative Mikroelektronik, Germany"}]},{"ORCID":"http:\/\/orcid.org\/0000-0002-8117-4357","authenticated-orcid":false,"given":"Tommaso","family":"Rizzi","sequence":"additional","affiliation":[{"name":"Material Research, IHP - Leibniz Institut fuer innovative Mikroelektronik, Germany"}]},{"ORCID":"http:\/\/orcid.org\/0009-0003-7733-8907","authenticated-orcid":false,"given":"Jianan","family":"Wen","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut fuer innovative Mikroelektronik, Germany"}]},{"ORCID":"http:\/\/orcid.org\/0000-0001-5133-7816","authenticated-orcid":false,"given":"Emilio","family":"P\u00e9rez-Bosch Quesada","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut fuer innovative Mikroelektronik, Germany"}]},{"ORCID":"http:\/\/orcid.org\/0000-0002-4675-9771","authenticated-orcid":false,"given":"Bakr","family":"Al Beattie","sequence":"additional","affiliation":[{"name":"Ruhr University Bochum, Germany"}]},{"ORCID":"http:\/\/orcid.org\/0000-0002-1484-6125","authenticated-orcid":false,"given":"Karlheinz","family":"Ochs","sequence":"additional","affiliation":[{"name":"Ruhr University Bochum, Germany"}]},{"ORCID":"http:\/\/orcid.org\/0000-0001-7545-9420","authenticated-orcid":false,"given":"Eduardo","family":"P\u00e9rez","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut fuer innovative Mikroelektronik, Germany"}]},{"ORCID":"http:\/\/orcid.org\/0009-0009-0393-2528","authenticated-orcid":false,"given":"Philip","family":"Ostrovskyy","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut fuer innovative Mikroelektronik, Germany"}]},{"ORCID":"http:\/\/orcid.org\/0000-0001-9147-0160","authenticated-orcid":false,"given":"Corrado","family":"Carta","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut fuer innovative Mikroelektronik, Germany"}]},{"ORCID":"http:\/\/orcid.org\/0000-0003-3698-2635","authenticated-orcid":false,"given":"Christian","family":"Wenger","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut fuer innovative Mikroelektronik, Germany"}]},{"ORCID":"http:\/\/orcid.org\/0000-0003-2674-2240","authenticated-orcid":false,"given":"Gerhard","family":"Kahmen","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut fuer innovative Mikroelektronik, Germany"}]}],"member":"320","published-online":{"date-parts":[[2024,1,25]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.13"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2023.3273520"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00286"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1049\/joe.2018.5234"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.2004.10971"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.5281\/zenodo.3333552"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.48550\/arXiv.2003.06471"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/DCIS51330.2020.9268652"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.3390\/electronics10060645"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2023.3244509"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2023.3268092"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-022-04992-8"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS52668.2021.9417070"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/DFT56152.2022.9962345"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063078"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ITC44778.2020.9325249"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1186\/s11671-020-03299-9"}],"event":{"name":"NANOARCH '23: 18th ACM International Symposium on Nanoscale Architectures","acronym":"NANOARCH '23","location":"Dresden Germany"},"container-title":["Proceedings of the 18th ACM International Symposium on Nanoscale Architectures"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3611315.3633273","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,25]],"date-time":"2024-01-25T18:09:59Z","timestamp":1706206199000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3611315.3633273"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,12,18]]},"references-count":18,"alternative-id":["10.1145\/3611315.3633273","10.1145\/3611315"],"URL":"http:\/\/dx.doi.org\/10.1145\/3611315.3633273","relation":{},"subject":[],"published":{"date-parts":[[2023,12,18]]},"assertion":[{"value":"2024-01-25","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}</enrichment>
    <enrichment key="opus_crossrefDocumentType">proceedings-article</enrichment>
    <enrichment key="opus_import_origin">crossref</enrichment>
    <enrichment key="opus_doiImportPopulated">PersonAuthorFirstName_1,PersonAuthorLastName_1,PersonAuthorIdentifierOrcid_1,PersonAuthorFirstName_2,PersonAuthorLastName_2,PersonAuthorIdentifierOrcid_2,PersonAuthorFirstName_3,PersonAuthorLastName_3,PersonAuthorIdentifierOrcid_3,PersonAuthorFirstName_4,PersonAuthorLastName_4,PersonAuthorIdentifierOrcid_4,PersonAuthorFirstName_5,PersonAuthorLastName_5,PersonAuthorIdentifierOrcid_5,PersonAuthorFirstName_6,PersonAuthorLastName_6,PersonAuthorIdentifierOrcid_6,PersonAuthorFirstName_7,PersonAuthorLastName_7,PersonAuthorIdentifierOrcid_7,PersonAuthorFirstName_8,PersonAuthorLastName_8,PersonAuthorIdentifierOrcid_8,PersonAuthorFirstName_9,PersonAuthorLastName_9,PersonAuthorIdentifierOrcid_9,PersonAuthorFirstName_10,PersonAuthorLastName_10,PersonAuthorIdentifierOrcid_10,PersonAuthorFirstName_11,PersonAuthorLastName_11,PersonAuthorIdentifierOrcid_11,EnrichmentConferenceTitle,EnrichmentConferencePlace,PublisherName,PublisherPlace,TitleMain_1,TitleParent_1,PageNumber,PageFirst,PageLast,PublishedYear</enrichment>
    <enrichment key="BTU">an der BTU erstellt / created at BTU</enrichment>
    <enrichment key="Referiert">Beitrag ist referiert / Article peer-reviewed</enrichment>
    <enrichment key="ConferencePlace">Dresden Germany</enrichment>
    <enrichment key="ConferenceTitle">NANOARCH '23: 18th ACM International Symposium on Nanoscale Architectures</enrichment>
    <enrichment key="opus.source">doi-import</enrichment>
    <enrichment key="Publikationsweg">Open Access</enrichment>
    <enrichment key="opus.doi.autoCreate">false</enrichment>
    <enrichment key="opus.urn.autoCreate">false</enrichment>
    <enrichment key="Fprofil">4 Künstliche Intelligenz und Sensorik / Artificial Intelligence and Sensor Technology</enrichment>
    <author>
      <firstName>Max</firstName>
      <lastName>Uhlmann</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Tommaso</firstName>
      <lastName>Rizzi</lastName>
    </author>
    <author>
      <firstName>Jianan</firstName>
      <lastName>Wen</lastName>
    </author>
    <author>
      <firstName>Emilio</firstName>
      <lastName>Pérez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Bakr</firstName>
      <lastName>Al Beattie</lastName>
    </author>
    <author>
      <firstName>Karlheinz</firstName>
      <lastName>Ochs</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Philip</firstName>
      <lastName>Ostrovskyy</lastName>
    </author>
    <author>
      <firstName>Corrado</firstName>
      <lastName>Carta</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Gerhard</firstName>
      <lastName>Kahmen</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Neural network</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
    <collection role="institutes" number="1122">FG Halbleitertechnologie</collection>
  </doc>
  <doc>
    <id>36422</id>
    <completedYear/>
    <publishedYear>2025</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>1</pageFirst>
    <pageLast>5</pageLast>
    <pageNumber>5</pageNumber>
    <edition/>
    <issue/>
    <volume/>
    <type>articler</type>
    <publisherName>Institute of Electrical and Electronics Engineers (IEEE)</publisherName>
    <publisherPlace>New York</publisherPlace>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2025-08-18</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">End-to-end design flow for resistive neural accelerators</title>
    <abstract language="eng">Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed towards leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP’s one-transistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators.</abstract>
    <parentTitle language="eng">IEEE transactions on computer-aided design of integrated circuits and systems</parentTitle>
    <identifier type="doi">10.1109/TCAD.2025.3597237</identifier>
    <identifier type="issn">0278-0070</identifier>
    <identifier type="issn">1937-4151</identifier>
    <enrichment key="Fprofil">4 Künstliche Intelligenz und Sensorik / Artificial Intelligence and Sensor Technology</enrichment>
    <enrichment key="opus_doi_flag">true</enrichment>
    <enrichment key="opus_import_data">{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,15]],"date-time":"2025-08-15T02:03:05Z","timestamp":1755223385067,"version":"3.43.0"},"reference-count":0,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","award":["434434223"],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."],"published-print":{"date-parts":[[2025]]},"DOI":"10.1109\/tcad.2025.3597237","type":"journal-article","created":{"date-parts":[[2025,8,8]],"date-time":"2025-08-08T18:39:56Z","timestamp":1754678396000},"page":"1-1","source":"Crossref","is-referenced-by-count":0,"title":["End-to-End Design Flow for Resistive Neural Accelerators"],"prefix":"10.1109","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-8625-2040","authenticated-orcid":false,"given":"Max","family":"Uhlmann","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8117-4357","authenticated-orcid":false,"given":"Tommaso","family":"Rizzi","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0009-0003-7733-8907","authenticated-orcid":false,"given":"Jianan","family":"Wen","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5133-7816","authenticated-orcid":false,"given":"Emilio P\u00e9rez-Bosch","family":"Quesada","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4675-9771","authenticated-orcid":false,"given":"Bakr Al","family":"Beattie","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1484-6125","authenticated-orcid":false,"given":"Karlheinz","family":"Ochs","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7545-9420","authenticated-orcid":false,"given":"Eduardo","family":"P\u00e9rez","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0009-0009-0393-2528","authenticated-orcid":false,"given":"Philip","family":"Ostrovskyy","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9147-0160","authenticated-orcid":false,"given":"Corrado","family":"Carta","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3698-2635","authenticated-orcid":false,"given":"Christian","family":"Wenger","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2674-2240","authenticated-orcid":false,"given":"Gerhard","family":"Kahmen","sequence":"additional","affiliation":[]}],"member":"263","container-title":["IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/43\/6917053\/11121349.pdf?arnumber=11121349","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,11]],"date-time":"2025-08-11T17:43:35Z","timestamp":1754934215000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11121349\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025]]},"references-count":0,"URL":"https:\/\/doi.org\/10.1109\/tcad.2025.3597237","relation":{},"ISSN":["0278-0070","1937-4151"],"issn-type":[{"value":"0278-0070","type":"print"},{"value":"1937-4151","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025]]}}}</enrichment>
    <enrichment key="opus_crossrefDocumentType">journal-article</enrichment>
    <enrichment key="local_crossrefLicence">https://creativecommons.org/licenses/by-nc-nd/4.0/</enrichment>
    <enrichment key="local_import_origin">crossref</enrichment>
    <enrichment key="local_doiImportPopulated">PersonAuthorFirstName_1,PersonAuthorLastName_1,PersonAuthorIdentifierOrcid_1,PersonAuthorFirstName_2,PersonAuthorLastName_2,PersonAuthorIdentifierOrcid_2,PersonAuthorFirstName_3,PersonAuthorLastName_3,PersonAuthorIdentifierOrcid_3,PersonAuthorFirstName_4,PersonAuthorLastName_4,PersonAuthorIdentifierOrcid_4,PersonAuthorFirstName_5,PersonAuthorLastName_5,PersonAuthorIdentifierOrcid_5,PersonAuthorFirstName_6,PersonAuthorLastName_6,PersonAuthorIdentifierOrcid_6,PersonAuthorFirstName_7,PersonAuthorLastName_7,PersonAuthorIdentifierOrcid_7,PersonAuthorFirstName_8,PersonAuthorLastName_8,PersonAuthorIdentifierOrcid_8,PersonAuthorFirstName_9,PersonAuthorLastName_9,PersonAuthorIdentifierOrcid_9,PersonAuthorFirstName_10,PersonAuthorLastName_10,PersonAuthorIdentifierOrcid_10,PersonAuthorFirstName_11,PersonAuthorLastName_11,PersonAuthorIdentifierOrcid_11,PublisherName,TitleMain_1,TitleParent_1,PageNumber,PageFirst,PageLast,PublishedYear,IdentifierIssn,Enrichmentlocal_crossrefLicence</enrichment>
    <enrichment key="BTU">an der BTU erstellt / created at BTU</enrichment>
    <enrichment key="Referiert">Beitrag ist referiert / Article peer-reviewed</enrichment>
    <enrichment key="opus.source">doi-import</enrichment>
    <enrichment key="opus.doi.autoCreate">false</enrichment>
    <enrichment key="opus.urn.autoCreate">false</enrichment>
    <licence>Creative Commons - CC BY-NC-ND - Namensnennung - Nicht kommerziell - Keine Bearbeitungen 4.0 International</licence>
    <author>
      <firstName>Max</firstName>
      <lastName>Uhlmann</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Tommaso</firstName>
      <lastName>Rizzi</lastName>
    </author>
    <author>
      <firstName>Jianan</firstName>
      <lastName>Wen</lastName>
    </author>
    <author>
      <firstName>Emilio Pérez-Bosch</firstName>
      <lastName>Quesada</lastName>
    </author>
    <author>
      <firstName>Bakr Al</firstName>
      <lastName>Beattie</lastName>
    </author>
    <author>
      <firstName>Karlheinz</firstName>
      <lastName>Ochs</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Philip</firstName>
      <lastName>Ostrovskyy</lastName>
    </author>
    <author>
      <firstName>Corrado</firstName>
      <lastName>Carta</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Gerhard</firstName>
      <lastName>Kahmen</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
    <collection role="institutes" number="1122">FG Halbleitertechnologie</collection>
  </doc>
</export-example>
