<?xml version="1.0" encoding="utf-8"?>
<export-example>
  <doc>
    <id>27031</id>
    <completedYear/>
    <publishedYear>2020</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject_ref</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation>IEEE</contributingCorporation>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-16</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Behavioral modeling of multilevel HfO2-based memristors for neuromorphic circuit simulation</title>
    <abstract language="eng">An artificial neural network based on resistive switching memristors is implemented and simulated in LTspice. The influence of memristor variability and the reduction of the continuous range of synaptic weights into a discrete set of conductance levels is analyzed. To do so, a behavioral model is proposed for multilevel resistive switching memristors based on Al-doped HfO2 dielectrics, and it is implemented in a spice based circuit simulator. The model provides an accurate description of the conductance in the different conductive states in addition to describe the device-to-device variability</abstract>
    <parentTitle language="eng">XXXV Conference on Design of Circuits and Integrated Systems (DCIS), Segovia, Spain</parentTitle>
    <identifier type="doi">10.1109/DCIS51330.2020.9268652</identifier>
    <enrichment key="BTU">an der BTU erstellt / created at BTU</enrichment>
    <enrichment key="opus.source">publish</enrichment>
    <enrichment key="opus.doi.autoCreate">false</enrichment>
    <enrichment key="opus.urn.autoCreate">false</enrichment>
    <enrichment key="Fprofil">4 Künstliche Intelligenz und Sensorik / Artificial Intelligence and Sensor Technology</enrichment>
    <author>
      <firstName>Antonio Javier</firstName>
      <lastName>Perez-Avila</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Gerardo</firstName>
      <lastName>Gonzalez-Cordero</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Mamathamba Kalishettyhalli</firstName>
      <lastName>Mahadevaiah</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Juan Bautista</firstName>
      <lastName>Roldan</lastName>
    </author>
    <author>
      <firstName>Francisco</firstName>
      <lastName>Jimenez-Molinos</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Multilevel switching</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>behavorial model</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
  </doc>
  <doc>
    <id>27064</id>
    <completedYear/>
    <publishedYear>2021</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber>17</pageNumber>
    <edition/>
    <issue>5</issue>
    <volume>10</volume>
    <type>articler</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-02-24</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells</title>
    <abstract language="eng">In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage&#13;
pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.</abstract>
    <parentTitle language="eng">Electronics</parentTitle>
    <identifier type="issn">2079-9292</identifier>
    <identifier type="doi">10.3390/electronics10050530</identifier>
    <enrichment key="BTU">an der BTU erstellt / created at BTU</enrichment>
    <enrichment key="Artikelnummer">530</enrichment>
    <enrichment key="opus.source">publish</enrichment>
    <enrichment key="Fprofil">4 Künstliche Intelligenz und Sensorik / Artificial Intelligence and Sensor Technology</enrichment>
    <author>
      <firstName>Stefan</firstName>
      <lastName>Pechmann</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Timo</firstName>
      <lastName>Mai</lastName>
    </author>
    <author>
      <firstName>Matthias</firstName>
      <lastName>Völkel</lastName>
    </author>
    <author>
      <firstName>Mamathamba Kalishettyhalli</firstName>
      <lastName>Mahadevaiah</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Marc</firstName>
      <lastName>Reichenbach</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Amelie</firstName>
      <lastName>Hagelauer</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Multilevel switching</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Programming circuit</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
  </doc>
  <doc>
    <id>27376</id>
    <completedYear/>
    <publishedYear>2021</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber>15</pageNumber>
    <edition/>
    <issue>9</issue>
    <volume>10</volume>
    <type>articler</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-05-03</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing</title>
    <abstract language="eng">Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8×8 vector-matrixmultiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters.</abstract>
    <parentTitle language="eng">Electronics (MDPI)</parentTitle>
    <identifier type="issn">2079-9292</identifier>
    <identifier type="doi">10.3390/electronics10091084</identifier>
    <enrichment key="BTU">an der BTU erstellt / created at BTU</enrichment>
    <enrichment key="Artikelnummer">1084</enrichment>
    <enrichment key="opus.source">publish</enrichment>
    <enrichment key="Fprofil">4 Künstliche Intelligenz und Sensorik / Artificial Intelligence and Sensor Technology</enrichment>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Antonio Javier</firstName>
      <lastName>Pérez-Ávila</lastName>
    </author>
    <author>
      <firstName>Rocío</firstName>
      <lastName>Romero-Zaliz</lastName>
    </author>
    <author>
      <firstName>Mamathamba Kalishettyhalli</firstName>
      <lastName>Mahadevaiah</lastName>
    </author>
    <author>
      <firstName>Emilio</firstName>
      <lastName>Pérez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Juan Bautista</firstName>
      <lastName>Roldan</lastName>
    </author>
    <author>
      <firstName>Francisco</firstName>
      <lastName>Jiménez-Molinos</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Multilevel switching</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>In-memory computing</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
  </doc>
  <doc>
    <id>27514</id>
    <completedYear/>
    <publishedYear>2021</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>2693</pageFirst>
    <pageLast>2698</pageLast>
    <pageNumber/>
    <edition/>
    <issue>6</issue>
    <volume>68</volume>
    <type>articler</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-05-25</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Variability and Energy Consumption Tradeoffs in Multilevel Programming of RRAM Arrays</title>
    <abstract language="eng">Achieving a reliable multi-level programming operation in resistive random access memory (RRAM) arrays is still a challenging task. In this work, we assessed the impact of the voltage step value used by the programming algorithm on the device-to-device (DTD) variability of the current distributions of four conductive levels and on the energy consumption featured by programming 4-kbit HfO2-based RRAM arrays. Two different write-verify algorithms were considered and compared, namely, the incremental gate voltage with verify algorithm (IGVVA) and the incremental step pulse with verify algorithm (ISPVA). By using the IGVVA, a main trade-off has to be taken into account since reducing the voltage step leads to a smaller DTD variability at the cost of a strong increase in the energy consumption. Although the ISPVA can not reduce the DTD variability as much as the IGVVA, its voltage step can be decreased in order to reduce the energy consumption with almost no impact on the DTD variability. Therefore, the final decision on which algorithm&#13;
to employ should be based on the specific application targeted for the RRAM array.</abstract>
    <parentTitle language="eng">IEEE Transactions on Electron Devices</parentTitle>
    <identifier type="issn">0018-9383</identifier>
    <identifier type="issn">1557-9646</identifier>
    <identifier type="doi">10.1109/TED.2021.3072868</identifier>
    <enrichment key="BTU">an der BTU erstellt / created at BTU</enrichment>
    <enrichment key="opus.source">publish</enrichment>
    <enrichment key="opus.doi.autoCreate">false</enrichment>
    <enrichment key="opus.urn.autoCreate">false</enrichment>
    <enrichment key="Fprofil">4 Künstliche Intelligenz und Sensorik / Artificial Intelligence and Sensor Technology</enrichment>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Mamathamba Kalishettyhalli</firstName>
      <lastName>Mahadevaiah</lastName>
    </author>
    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Multilevel switching</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>HfO2</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
  </doc>
</export-example>
