<?xml version="1.0" encoding="utf-8"?>
<export-example>
  <doc>
    <id>27134</id>
    <completedYear/>
    <publishedYear>2021</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber>13</pageNumber>
    <edition/>
    <issue>6</issue>
    <volume>10</volume>
    <type>articler</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2021-03-11</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems</title>
    <abstract language="eng">In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of&#13;
experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance&#13;
levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.</abstract>
    <parentTitle language="eng">Electronics (MDPI)</parentTitle>
    <identifier type="issn">2079-9292</identifier>
    <identifier type="doi">10.3390/electronics10060645</identifier>
    <enrichment key="BTU">an der BTU erstellt / created at BTU</enrichment>
    <enrichment key="Artikelnummer">645</enrichment>
    <enrichment key="opus.source">publish</enrichment>
    <enrichment key="opus.doi.autoCreate">false</enrichment>
    <enrichment key="opus.urn.autoCreate">false</enrichment>
    <enrichment key="Fprofil">4 Künstliche Intelligenz und Sensorik / Artificial Intelligence and Sensor Technology</enrichment>
    <author>
      <firstName>Emilio</firstName>
      <lastName>Pérez-Bosch Quesada</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Rocío</firstName>
      <lastName>Romero-Zaliz</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Mamathamba Kalishettyhalli</firstName>
      <lastName>Mahadevaiah</lastName>
    </author>
    <author>
      <firstName>John</firstName>
      <lastName>Reuben</lastName>
    </author>
    <author>
      <firstName>Markus Andreas</firstName>
      <lastName>Schubert</lastName>
    </author>
    <author>
      <firstName>Francisco</firstName>
      <lastName>Jiménez-Molinos</lastName>
    </author>
    <author>
      <firstName>Juan Bautista</firstName>
      <lastName>Roldán</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>multilevel switching</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>compact modeling</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Verilog-A</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
  </doc>
</export-example>
