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  <doc>
    <id>29207</id>
    <completedYear/>
    <publishedYear>2022</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>83</pageFirst>
    <pageLast>88</pageLast>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject_ref</type>
    <publisherName/>
    <publisherPlace/>
    <creatingCorporation/>
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    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2022-08-02</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Analytical Calculation of Inference in Memristor-based Stochastic Artificial Neural Networks</title>
    <abstract language="eng">The impact of artificial intelligence on human life&#13;
has increased significantly in recent years. However, as the&#13;
complexity of problems rose aswell, increasing system features&#13;
for such amount of data computation became troublesome due&#13;
to the von Neumann’s computer architecture. Neuromorphic&#13;
computing aims to solve this problem by mimicking the parallel&#13;
computation of a human brain. For this approach, memristive&#13;
devices are used to emulate the synapses of a human brain. Yet,&#13;
common simulations of hardware based networks require time&#13;
consuming Monte-Carlo simulations to take into account the&#13;
stochastic switching of memristive devices. This work presents&#13;
an alternative concept making use of the convolution of the&#13;
probability distribution functions (PDF) of memristor currents&#13;
by its equivalent multiplication in Fourier domain. An artificial&#13;
neural network is accordingly implemented to perform the&#13;
inference stage with handwritten digits.</abstract>
    <parentTitle language="eng">29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES), 23-24 June 2022 , Wrocław, Poland</parentTitle>
    <identifier type="doi">10.23919/MIXDES55591.2022.9838321</identifier>
    <identifier type="isbn">978-83-63578-22-0</identifier>
    <identifier type="isbn">978-83-63578-21-3</identifier>
    <identifier type="isbn">978-1-6654-6176-4</identifier>
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    <author>
      <firstName>Nicolas</firstName>
      <lastName>Bogun</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Alexander</firstName>
      <lastName>Kloes</lastName>
    </author>
    <author>
      <firstName>Mike</firstName>
      <lastName>Schwarz</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>neural network</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
  </doc>
  <doc>
    <id>29886</id>
    <completedYear/>
    <publishedYear>2023</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>360</pageFirst>
    <pageLast>365</pageLast>
    <pageNumber/>
    <edition/>
    <issue>1</issue>
    <volume>70</volume>
    <type>articler</type>
    <publisherName/>
    <publisherPlace/>
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    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2023-01-04</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Parameter Extraction Methods for Assessing Device-to-Device and Cycle-to-Cycle Variability of Memristive Devices at Wafer Scale</title>
    <abstract language="eng">The stochastic nature of the resistive switching (RS) process in memristive devices makes device-to-device (DTD) and cycle-to-cycle (CTC) variabilities relevant magnitudes to be quantified and modeled. To accomplish this aim, robust and reliable parameter extraction methods must be employed. In this work, four different extraction methods were used at the production level (over all the 108 devices integrated on 200-mm wafers manufactured in the IHP 130-nm CMOS technology) in order to obtain the corresponding collection of forming, reset, and set switching voltages. The statistical analysis of the experimental data (mean and standard deviation (SD) values) was plotted by using heat maps, which provide a good summary of the whole data at a glance and, in addition, an easy manner to detect inhomogeneities in the fabrication process.</abstract>
    <parentTitle language="eng">IEEE Transactions on Electron Devices</parentTitle>
    <identifier type="issn">0018-9383</identifier>
    <identifier type="doi">10.1109/TED.2022.3224886</identifier>
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    <enrichment key="opus.source">publish</enrichment>
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    <enrichment key="Fprofil">4 Künstliche Intelligenz und Sensorik / Artificial Intelligence and Sensor Technology</enrichment>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>David</firstName>
      <lastName>Maldonado</lastName>
    </author>
    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Mamathamba Kalishettyhalli</firstName>
      <lastName>Mahadevaiah</lastName>
    </author>
    <author>
      <firstName>Francisco</firstName>
      <lastName>Jimenez-Molinos</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>memristive device</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>cycle-to-cycle variability</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>device-to-device variability</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
  </doc>
  <doc>
    <id>34870</id>
    <completedYear/>
    <publishedYear>2024</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>2391</pageFirst>
    <pageLast>2394</pageLast>
    <pageNumber>4</pageNumber>
    <edition/>
    <issue>12</issue>
    <volume>45</volume>
    <type>articler</type>
    <publisherName>Institute of Electrical and Electronics Engineers (IEEE)</publisherName>
    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2024-12-12</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">Forming and resistive switching of HfO₂-based RRAM devices at cryogenic temperature</title>
    <abstract language="eng">Reliable data storage technologies able to operate at cryogenic temperatures are critical to implement scalable quantum computers and develop deep-space exploration systems, among other applications. Their scarce availability is pushing towards the development of emerging memories that can perform such storage in a non-volatile fashion. Resistive Random-Access Memories (RRAM) have demonstrated their switching capabilities down to 4K. However, their operability at lower temperatures still remain as a challenge. In this work, we demonstrate for the first time the forming and resistive switching capabilities of CMOS-compatible RRAM devices at 1.4K. The HfO2-based devices are deployed following an array of 1-transistor-1-resistor (1T1R) cells. Their switching performance at 1.4K was also tested in the multilevel-cell (MLC) approach, storing up to 4 resistance levels per cell.</abstract>
    <parentTitle language="eng">IEEE Electron Device Letters</parentTitle>
    <identifier type="doi">10.1109/LED.2024.3485873</identifier>
    <identifier type="issn">0741-3106</identifier>
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    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
    </author>
    <submitter>
      <firstName>Wenger</firstName>
      <lastName>Christian</lastName>
    </submitter>
    <author>
      <firstName>Alberto</firstName>
      <lastName>Mistroni</lastName>
    </author>
    <author>
      <firstName>Ruolan</firstName>
      <lastName>Jia</lastName>
    </author>
    <author>
      <firstName>Keerthi</firstName>
      <lastName>Dorai Swamy Reddy</lastName>
    </author>
    <author>
      <firstName>Felix</firstName>
      <lastName>Reichmann</lastName>
    </author>
    <author>
      <firstName>Helena</firstName>
      <lastName>Castan</lastName>
    </author>
    <author>
      <firstName>Salvador</firstName>
      <lastName>Dueñas</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Perez</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
  </doc>
  <doc>
    <id>34340</id>
    <completedYear/>
    <publishedYear>2023</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst>1</pageFirst>
    <pageLast>6</pageLast>
    <pageNumber>6</pageNumber>
    <edition/>
    <issue/>
    <volume/>
    <type>conferenceobject_ref</type>
    <publisherName>ACM</publisherName>
    <publisherPlace>New York, NY, USA</publisherPlace>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2024-10-29</completedDate>
    <publishedDate>--</publishedDate>
    <thesisDateAccepted>--</thesisDateAccepted>
    <title language="eng">LUT-based RRAM model for neural accelerator circuit simulation</title>
    <abstract language="eng">Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices’ models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP’s 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis.</abstract>
    <parentTitle language="eng">Proceedings of the 18th ACM International Symposium on Nanoscale Architectures</parentTitle>
    <identifier type="doi">10.1145/3611315.3633273</identifier>
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    <author>
      <firstName>Max</firstName>
      <lastName>Uhlmann</lastName>
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    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Tommaso</firstName>
      <lastName>Rizzi</lastName>
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    <author>
      <firstName>Jianan</firstName>
      <lastName>Wen</lastName>
    </author>
    <author>
      <firstName>Emilio</firstName>
      <lastName>Pérez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Bakr</firstName>
      <lastName>Al Beattie</lastName>
    </author>
    <author>
      <firstName>Karlheinz</firstName>
      <lastName>Ochs</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Philip</firstName>
      <lastName>Ostrovskyy</lastName>
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    <author>
      <firstName>Corrado</firstName>
      <lastName>Carta</lastName>
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    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
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    <author>
      <firstName>Gerhard</firstName>
      <lastName>Kahmen</lastName>
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    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Neural network</value>
    </subject>
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  <doc>
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    <volume>201</volume>
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    <title language="eng">Stochastic switching of memristors and consideration in circuit simulation</title>
    <abstract language="eng">We explore the stochastic switching of oxide-based memristive devices by using the Stanford model for circuit simulation. From measurements, the device-to-device (D2D) and cycle-to-cycle (C2C) statistical variation is extracted. In the low-resistive state (LRS) dispersion by D2D variability is dominant. In the high-resistive state&#13;
(HRS) C2C dispersion becomes the main source of fluctuation. A statistical procedure for the extraction of parameters of the compact model is presented. Thereby, in a circuit simulation the typical D2D and C2C fluctuations of the current–voltage (I-V) characteristics can be emulated by extracting statistical parameters of key model parameters. The statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of memory cells or can be used to emulate the synaptic behavior of these devices in artificial neural networks realized by a crossbar array of memristors.</abstract>
    <parentTitle language="eng">Solid State Electronics</parentTitle>
    <identifier type="issn">0038-1101</identifier>
    <identifier type="doi">10.1016/j.sse.2023.108606</identifier>
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    <author>
      <firstName>Alexander</firstName>
      <lastName>Kloes</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Carl</firstName>
      <lastName>Bischoff</lastName>
    </author>
    <author>
      <firstName>Jakob</firstName>
      <lastName>Leise</lastName>
    </author>
    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>memristive device</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>variability</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
  </doc>
  <doc>
    <id>30620</id>
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    <publishedYear>2023</publishedYear>
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    <language>eng</language>
    <pageFirst>2009</pageFirst>
    <pageLast>2014</pageLast>
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    <edition/>
    <issue>4</issue>
    <volume>70</volume>
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    <completedDate>2023-03-31</completedDate>
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    <title language="eng">Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing</title>
    <abstract language="eng">Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices’ nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.</abstract>
    <parentTitle language="eng">IEEE Transactions on Electron Devices</parentTitle>
    <identifier type="issn">0018-9383</identifier>
    <identifier type="doi">10.1109/TED.2023.3244509</identifier>
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    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
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    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Mamathamba Kalishettyhalli</firstName>
      <lastName>Mahadevaiah</lastName>
    </author>
    <author>
      <firstName>Tommaso</firstName>
      <lastName>Rizzi</lastName>
    </author>
    <author>
      <firstName>Jianan</firstName>
      <lastName>Wen</lastName>
    </author>
    <author>
      <firstName>Markus</firstName>
      <lastName>Ulbricht</lastName>
    </author>
    <author>
      <firstName>Milos</firstName>
      <lastName>Krstic</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Vector Matrix Multiplication</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>variability</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
  </doc>
  <doc>
    <id>31349</id>
    <completedYear/>
    <publishedYear>2023</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume>209</volume>
    <type>articler</type>
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    <publisherPlace/>
    <creatingCorporation/>
    <contributingCorporation/>
    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2023-09-21</completedDate>
    <publishedDate>--</publishedDate>
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    <title language="eng">Efficient circuit simulation of a memristive crossbar array with synaptic weight variability</title>
    <abstract language="eng">In this paper, we present a method for highly-efficient circuit simulation of a hardware-based artificial neural network realized in a memristive crossbar array. The statistical variability of the devices is considered by a noise-based simulation technique. For the simulation of a crossbar array with 8 synaptic weights in Cadence Virtuoso the new approach shows a more than 200x speed improvement compared to a Monte Carlo approach, yielding the same results. In addition, first results of an ANN with more than 15,000 memristive devices classifying test data of the MNIST dataset are shown, for which the speed improvement is expected to be several orders of magnitude. Furthermore, the influence on the classification of parasitic resistances of the connection lines in the crossbar is shown.</abstract>
    <parentTitle language="eng">Solid State Electronics</parentTitle>
    <identifier type="issn">0038-1101</identifier>
    <identifier type="doi">10.1016/j.sse.2023.108760</identifier>
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    <author>
      <firstName>Nadine</firstName>
      <lastName>Dersch</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
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    <author>
      <firstName>Christian</firstName>
      <lastName>Roemer</lastName>
    </author>
    <author>
      <firstName>Mike</firstName>
      <lastName>Schwarz</lastName>
    </author>
    <author>
      <firstName>Alexander</firstName>
      <lastName>Kloes</lastName>
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    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Neural network</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
  </doc>
  <doc>
    <id>31351</id>
    <completedYear/>
    <publishedYear>2023</publishedYear>
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    <language>eng</language>
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    <pageLast/>
    <pageNumber>5</pageNumber>
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    <completedDate>2023-09-21</completedDate>
    <publishedDate>--</publishedDate>
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    <title language="eng">One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing</title>
    <abstract language="eng">The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications.</abstract>
    <parentTitle language="eng">21st IEEE Interregional NEWCAS Conference (NEWCAS)</parentTitle>
    <identifier type="doi">10.1109/NEWCAS57931.2023.10198073</identifier>
    <identifier type="isbn">979-8-3503-0024-6</identifier>
    <identifier type="isbn">979-8-3503-0025-3</identifier>
    <identifier type="issn">2474-9672</identifier>
    <identifier type="issn">2472-467X</identifier>
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    <author>
      <firstName>Max</firstName>
      <lastName>Uhlmann</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Emilio</firstName>
      <lastName>Pérez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Markus</firstName>
      <lastName>Fritscher</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Markus Andreas</firstName>
      <lastName>Schubert</lastName>
    </author>
    <author>
      <firstName>Marc</firstName>
      <lastName>Reichenbach</lastName>
    </author>
    <author>
      <firstName>Philip</firstName>
      <lastName>Ostrovskyy</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Gerhard</firstName>
      <lastName>Kahmen</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>In-Memory Computing</value>
    </subject>
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  <doc>
    <id>32224</id>
    <completedYear/>
    <publishedYear>2023</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber/>
    <edition/>
    <issue/>
    <volume>17</volume>
    <type>articler</type>
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    <completedDate>2023-12-20</completedDate>
    <publishedDate>--</publishedDate>
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    <title language="eng">TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance</title>
    <abstract language="eng">We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics.</abstract>
    <parentTitle language="eng">Frontiers in Neuroscience</parentTitle>
    <identifier type="issn">1662-4548</identifier>
    <identifier type="doi">10.3389/fnins.2023.1271956</identifier>
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    <enrichment key="Artikelnummer">1271956</enrichment>
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    <author>
      <firstName>David</firstName>
      <lastName>Maldonado</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Antonio</firstName>
      <lastName>Cantudo</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Rocio</firstName>
      <lastName>Romero-Zaliz</lastName>
    </author>
    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Mamathamba Kalishettyhalli</firstName>
      <lastName>Mahadevaiah</lastName>
    </author>
    <author>
      <firstName>Francisco</firstName>
      <lastName>Jimenez-Molinos</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Juan Bautista</firstName>
      <lastName>Roldan</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Neural network</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
  </doc>
  <doc>
    <id>32225</id>
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    <publishedYear>2023</publishedYear>
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    <language>eng</language>
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    <pageNumber>4</pageNumber>
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    <completedDate>2023-12-20</completedDate>
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    <title language="eng">Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing</title>
    <abstract language="eng">This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications.&#13;
Index Terms—radiation-hard, hardness-by-design, memristive&#13;
devices, Enclosed Layout Transistor, in-memory computing</abstract>
    <parentTitle language="eng">14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023</parentTitle>
    <identifier type="doi">10.1109/CDE58627.2023.10339525</identifier>
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    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
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    <author>
      <firstName>Tommaso</firstName>
      <lastName>Rizzi</lastName>
    </author>
    <author>
      <firstName>Aditya</firstName>
      <lastName>Gupta</lastName>
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    <author>
      <firstName>Mamathamba Kalishettyhalli</firstName>
      <lastName>Mahadevaiah</lastName>
    </author>
    <author>
      <firstName>Andreas</firstName>
      <lastName>Schubert</lastName>
    </author>
    <author>
      <firstName>Stefan</firstName>
      <lastName>Pechmann</lastName>
    </author>
    <author>
      <firstName>Ruolan</firstName>
      <lastName>Jia</lastName>
    </author>
    <author>
      <firstName>Max</firstName>
      <lastName>Uhlmann</lastName>
    </author>
    <author>
      <firstName>Amelie</firstName>
      <lastName>Hagelauer</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
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  <doc>
    <id>32226</id>
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    <publishedYear>2023</publishedYear>
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    <pageFirst/>
    <pageLast/>
    <pageNumber>5</pageNumber>
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    <completedDate>2023-12-20</completedDate>
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    <title language="eng">A comparison of resistive switching parameters for memristive devices with HfO2 monolayers and Al2O3/HfO2 bilayers at the wafer scale</title>
    <abstract language="eng">Memristive devices integrated in 200 mm wafers&#13;
manufactured in 130 nm CMOS technology with two different&#13;
dielectrics, namely, a HfO2 monolayer and an Al2O3/HfO2 bilayer,&#13;
have been measured. The cycle-to-cycle (C2C) and device-todevice (D2D) variability have been analyzed at the wafer scale using different numerical methods to extract the set (Vset) and reset (Vreset) voltages. Some interesting differences between both technologies were found in terms of switching characteristics</abstract>
    <parentTitle language="eng">14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023</parentTitle>
    <identifier type="doi">10.1109/CDE58627.2023.10339417</identifier>
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    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
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      <firstName>Christian</firstName>
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    <author>
      <firstName>David</firstName>
      <lastName>Maldonado</lastName>
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    <author>
      <firstName>Mamathamba Kalishettyhalli</firstName>
      <lastName>Mahadevaiah</lastName>
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    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
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    <author>
      <firstName>Antonio</firstName>
      <lastName>Cantudo</lastName>
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    <author>
      <firstName>Francisco</firstName>
      <lastName>Jimenez-Molinos</lastName>
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    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Juan Bautista</firstName>
      <lastName>Roldan</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
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  <doc>
    <id>36422</id>
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    <publishedYear>2025</publishedYear>
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    <language>eng</language>
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    <pageLast>5</pageLast>
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    <publisherPlace>New York</publisherPlace>
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    <completedDate>2025-08-18</completedDate>
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    <title language="eng">End-to-end design flow for resistive neural accelerators</title>
    <abstract language="eng">Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed towards leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP’s one-transistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators.</abstract>
    <parentTitle language="eng">IEEE transactions on computer-aided design of integrated circuits and systems</parentTitle>
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      <firstName>Bakr Al</firstName>
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      <firstName>Karlheinz</firstName>
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      <firstName>Eduardo</firstName>
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      <language>eng</language>
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      <value>RRAM</value>
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