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    <completedDate>2024-10-29</completedDate>
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    <title language="eng">LUT-based RRAM model for neural accelerator circuit simulation</title>
    <abstract language="eng">Neural hardware accelerators have been proven to be energy-efficient when used to solve tasks which can be mapped into an artificial neural network (ANN) structure. Resistive random-access memories (RRAMs) are currently under investigation together with several different memristive devices as promising technologies to build such accelerators combined together with complementary metal-oxide semiconductor (CMOS)-technologies in integrated circuits (ICs). While many research groups are actively developing sophisticated physical-based representations to better understand the underlying phenomena characterizing these devices, not much work has been dedicated to exploit the trade-off between simulation time and accuracy in the definition of low computational demanding models suitable to be used at many abstraction layers. Indeed, the design of complex mixed-signal systems as a neural hardware accelerators requires frequent interaction between the application- and the circuit-level that can be enabled only with the support of accurate and fast-simulating devices’ models. In this work, we propose a solution to fill the aforementioned gap with a lookup table (LUT)-based Verilog-A model of IHP’s 1-transistor-1-RRAM (1T1R) cell. In addition, the implementation challenges of conveying the communication between the abstract ANN simulation and the circuital analysis are tackled with a design flow for resistive neural hardware accelerators that features a custom Python wrapper. As a demonstration of the proposed design flow and 1T1R model, an ANN for the MNIST handwritten digit recognition task is assessed with the last layer verified in circuit simulation. The obtained recognition confidence intervals show a considerable discrepancy between the purely application-level PyTorch simulation and the proposed design flow which spans across the abstraction layers down to the circuital analysis.</abstract>
    <parentTitle language="eng">Proceedings of the 18th ACM International Symposium on Nanoscale Architectures</parentTitle>
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    <author>
      <firstName>Max</firstName>
      <lastName>Uhlmann</lastName>
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    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Tommaso</firstName>
      <lastName>Rizzi</lastName>
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    <author>
      <firstName>Jianan</firstName>
      <lastName>Wen</lastName>
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    <author>
      <firstName>Emilio</firstName>
      <lastName>Pérez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Bakr</firstName>
      <lastName>Al Beattie</lastName>
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    <author>
      <firstName>Karlheinz</firstName>
      <lastName>Ochs</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Philip</firstName>
      <lastName>Ostrovskyy</lastName>
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    <author>
      <firstName>Corrado</firstName>
      <lastName>Carta</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Gerhard</firstName>
      <lastName>Kahmen</lastName>
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    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Neural network</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
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    <language>eng</language>
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    <completedDate>2023-12-20</completedDate>
    <publishedDate>--</publishedDate>
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    <title language="eng">TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance</title>
    <abstract language="eng">We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics.</abstract>
    <parentTitle language="eng">Frontiers in Neuroscience</parentTitle>
    <identifier type="issn">1662-4548</identifier>
    <identifier type="doi">10.3389/fnins.2023.1271956</identifier>
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    <enrichment key="Artikelnummer">1271956</enrichment>
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    <enrichment key="Fprofil">4 Künstliche Intelligenz und Sensorik / Artificial Intelligence and Sensor Technology</enrichment>
    <author>
      <firstName>David</firstName>
      <lastName>Maldonado</lastName>
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    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
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    <author>
      <firstName>Antonio</firstName>
      <lastName>Cantudo</lastName>
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    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
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    <author>
      <firstName>Rocio</firstName>
      <lastName>Romero-Zaliz</lastName>
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    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
    </author>
    <author>
      <firstName>Mamathamba Kalishettyhalli</firstName>
      <lastName>Mahadevaiah</lastName>
    </author>
    <author>
      <firstName>Francisco</firstName>
      <lastName>Jimenez-Molinos</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Juan Bautista</firstName>
      <lastName>Roldan</lastName>
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    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Neural network</value>
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    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
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    <id>32226</id>
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    <publishedYear>2023</publishedYear>
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    <completedDate>2023-12-20</completedDate>
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    <title language="eng">A comparison of resistive switching parameters for memristive devices with HfO2 monolayers and Al2O3/HfO2 bilayers at the wafer scale</title>
    <abstract language="eng">Memristive devices integrated in 200 mm wafers&#13;
manufactured in 130 nm CMOS technology with two different&#13;
dielectrics, namely, a HfO2 monolayer and an Al2O3/HfO2 bilayer,&#13;
have been measured. The cycle-to-cycle (C2C) and device-todevice (D2D) variability have been analyzed at the wafer scale using different numerical methods to extract the set (Vset) and reset (Vreset) voltages. Some interesting differences between both technologies were found in terms of switching characteristics</abstract>
    <parentTitle language="eng">14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023</parentTitle>
    <identifier type="doi">10.1109/CDE58627.2023.10339417</identifier>
    <identifier type="isbn">979-8-3503-0240-0</identifier>
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    <enrichment key="Fprofil">4 Künstliche Intelligenz und Sensorik / Artificial Intelligence and Sensor Technology</enrichment>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
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    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
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    <author>
      <firstName>David</firstName>
      <lastName>Maldonado</lastName>
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    <author>
      <firstName>Mamathamba Kalishettyhalli</firstName>
      <lastName>Mahadevaiah</lastName>
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    <author>
      <firstName>Emilio</firstName>
      <lastName>Perez-Bosch Quesada</lastName>
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    <author>
      <firstName>Antonio</firstName>
      <lastName>Cantudo</lastName>
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    <author>
      <firstName>Francisco</firstName>
      <lastName>Jimenez-Molinos</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Juan Bautista</firstName>
      <lastName>Roldan</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
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    <id>33128</id>
    <completedYear/>
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    <language>eng</language>
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    <completedDate>2024-04-02</completedDate>
    <publishedDate>--</publishedDate>
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    <title language="eng">A current mirror Based read circuit design with multi-level capability for resistive switching deviceb</title>
    <abstract language="eng">This paper presents a read circuit design for resistive memory cells based on current mirrors. The circuit utilizes high-precision current mirrors and reference cells to determine the state of resistive memory using comparators. It offers a high degree in adaptability in terms of both resistance range and number of levels. Special emphasis was put on device protection to prevent accidental programming of the memory during read operations. The realized circuit can resolve eight states with a resolution of up to 1 k Ω, realizing a digitization of the analog memory information. Furthermore, the integration in a complete memory macro is shown. The circuit was realized in a 130 nm-process but can easily be adapted to other processes and resistive memory technologies.</abstract>
    <parentTitle language="eng">2024 International Conference on Electronics, Information, and Communication (ICEIC)</parentTitle>
    <identifier type="doi">10.1109/ICEIC61013.2024.10457188</identifier>
    <identifier type="isbn">979-8-3503-7188-8</identifier>
    <identifier type="issn">2767-7699</identifier>
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    <enrichment key="opus.source">publish</enrichment>
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    <enrichment key="Fprofil">4 Künstliche Intelligenz und Sensorik / Artificial Intelligence and Sensor Technology</enrichment>
    <author>
      <firstName>Stefan</firstName>
      <lastName>Pechmann</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Amelie</firstName>
      <lastName>Hagelauer</lastName>
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    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>memristive device</value>
    </subject>
    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
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  <doc>
    <id>34706</id>
    <completedYear/>
    <publishedYear>2024</publishedYear>
    <thesisYearAccepted/>
    <language>eng</language>
    <pageFirst/>
    <pageLast/>
    <pageNumber>9</pageNumber>
    <edition/>
    <issue/>
    <volume>97</volume>
    <type>articler</type>
    <publisherName>Springer Science and Business Media LLC</publisherName>
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    <belongsToBibliography>0</belongsToBibliography>
    <completedDate>2024-11-25</completedDate>
    <publishedDate>--</publishedDate>
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    <title language="eng">Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance</title>
    <abstract language="eng">Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2   dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO2   dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.</abstract>
    <parentTitle language="eng">The European Physical Journal B</parentTitle>
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The devices in 130\u00a0nm technology have shown lower number of high pristine state current devices per die in comparison to the 250\u00a0nm technology. For the 130\u00a0nm technology, the forming voltage is reduced due to the decrease of &lt;jats:inline-formula&gt;&lt;jats:alternatives&gt;&lt;jats:tex-math&gt;$$\\hbox {HfO}_2$$&lt;\/jats:tex-math&gt;&lt;mml:math xmlns:mml=\"http:\/\/www.w3.org\/1998\/Math\/MathML\"&gt;\n                    &lt;mml:msub&gt;\n                      &lt;mml:mtext&gt;HfO&lt;\/mml:mtext&gt;\n                      &lt;mml:mn&gt;2&lt;\/mml:mn&gt;\n                    &lt;\/mml:msub&gt;\n                  &lt;\/mml:math&gt;&lt;\/jats:alternatives&gt;&lt;\/jats:inline-formula&gt; dielectric thickness from 8\u00a0nm to 5\u00a0nm. Additionally, 5% Al-doped 4\u00a0nm &lt;jats:inline-formula&gt;&lt;jats:alternatives&gt;&lt;jats:tex-math&gt;$$\\hbox {HfO}_2$$&lt;\/jats:tex-math&gt;&lt;mml:math xmlns:mml=\"http:\/\/www.w3.org\/1998\/Math\/MathML\"&gt;\n                    &lt;mml:msub&gt;\n                      &lt;mml:mtext&gt;HfO&lt;\/mml:mtext&gt;\n                      &lt;mml:mn&gt;2&lt;\/mml:mn&gt;\n                    &lt;\/mml:msub&gt;\n                  &lt;\/mml:math&gt;&lt;\/jats:alternatives&gt;&lt;\/jats:inline-formula&gt; dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250\u00a0nm and 130\u00a0nm technologies are compared, where 130\u00a0nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250\u00a0nm technology.&lt;\/jats:p&gt;\n              &lt;\/jats:sec&gt;&lt;jats:sec&gt;\n                &lt;jats:title&gt;Graphical abstract&lt;\/jats:title&gt;\n                \n              &lt;\/jats:sec&gt;","DOI":"10.1140\/epjb\/s10051-024-00821-1","type":"journal-article","created":{"date-parts":[[2024,11,20]],"date-time":"2024-11-20T10:24:50Z","timestamp":1732098290000},"update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance"],"prefix":"10.1140","volume":"97","author":[{"ORCID":"http:\/\/orcid.org\/0000-0001-5260-7929","authenticated-orcid":false,"given":"Keerthi","family":"Dorai Swamy Reddy","sequence":"first","affiliation":[]},{"given":"Eduardo","family":"P\u00e9rez","sequence":"additional","affiliation":[]},{"given":"Andrea","family":"Baroni","sequence":"additional","affiliation":[]},{"given":"Mamathamba Kalishettyhalli","family":"Mahadevaiah","sequence":"additional","affiliation":[]},{"given":"Steffen","family":"Marschmeyer","sequence":"additional","affiliation":[]},{"given":"Mirko","family":"Fraschke","sequence":"additional","affiliation":[]},{"given":"Marco","family":"Lisker","sequence":"additional","affiliation":[]},{"given":"Christian","family":"Wenger","sequence":"additional","affiliation":[]},{"given":"Andreas","family":"Mai","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2024,11,20]]},"reference":[{"issue":"2","key":"821_CR1","doi-asserted-by":"publisher","first-page":"41","DOI":"10.1109\/MCSE.2017.29","volume":"19","author":"TN Theis","year":"2017","unstructured":"T.N. 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    <author>
      <firstName>Keerthi</firstName>
      <lastName>Dorai Swamy Reddy</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Andrea</firstName>
      <lastName>Baroni</lastName>
    </author>
    <author>
      <firstName>Mamathamba Kalishettyhalli</firstName>
      <lastName>Mahadevaiah</lastName>
    </author>
    <author>
      <firstName>Steffen</firstName>
      <lastName>Marschmeyer</lastName>
    </author>
    <author>
      <firstName>Mirko</firstName>
      <lastName>Fraschke</lastName>
    </author>
    <author>
      <firstName>Marco</firstName>
      <lastName>Lisker</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Andreas</firstName>
      <lastName>Mai</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
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    <pageNumber>11</pageNumber>
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    <volume>13</volume>
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    <publishedDate>2024-07-05</publishedDate>
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    <title language="eng">On the asymmetry of Resistive Switching Transitions</title>
    <abstract language="eng">In this study, the resistive switching phenomena in TiN/Ti/HfO2/Ti metal–insulator–metal stacks is investigated, mainly focusing on the analysis of set and reset transitions. The electrical measurements in a wide temperature range reveal that the switching transitions require less voltage (and thus, less energy) as temperature rises, with the reset process being much more temperature sensitive. The main conduction mechanism in both resistance states is Space-charge-limited Conduction, but the high conductivity state also shows Schottky emission, explaining its temperature dependence. Moreover, the temporal evolution of these transitions reveals clear differences between them, as their current transient response is completely different. While the set is sudden, the reset process development is clearly non-linear, closely resembling a sigmoid function. This asymmetry between switching processes is of extreme importance in the manipulation and control of the multi-level characteristics and has clear implications in the possible applications of resistive switching devices in neuromorphic computing.</abstract>
    <parentTitle language="eng">Electronics</parentTitle>
    <identifier type="issn">2079-9292</identifier>
    <identifier type="doi">10.3390/electronics13132639</identifier>
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    <author>
      <firstName>Guillermo</firstName>
      <lastName>Vinuesa</lastName>
    </author>
    <author>
      <firstName>Héctor</firstName>
      <lastName>García</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Ignacio</firstName>
      <lastName>Íñiguez de la Torre</lastName>
    </author>
    <author>
      <firstName>Tomás</firstName>
      <lastName>González</lastName>
    </author>
    <author>
      <firstName>Salvador</firstName>
      <lastName>Dueñas</lastName>
    </author>
    <author>
      <firstName>Helena</firstName>
      <lastName>Castán</lastName>
    </author>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>resistive switching</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>memristor</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>transient</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>temperature dependence</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>low power consumption</value>
    </subject>
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  </doc>
  <doc>
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    <issue>21</issue>
    <volume>MA2024-01</volume>
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    <title language="eng">Effect of the temperature on the performance and dynamic behavior of HfO2-Based Rram Devices</title>
    <abstract language="eng">Over the past decades, the demand for semiconductor memory devices has been steadily increasing, and is currently experiencing an unprecedented boost due to the development and expansion of artificial intelligence. Among emerging high-density non-volatile memories, resistive random-access memory (RRAM) is one of the best recourses for all kind of applications, such as neuromorphic computing or hardware security [1]. Although many materials have been evaluated for RRAM development, some of them with excellent results, HfO2 is one of the established materials in CMOS domain due to its compatibility with standard materials and processes [2].&#13;
 The main goal of this work is to study the switching capability and stability of HfO2-based RRAMs, as well as to explore their ability in the field of analogue applications, by analyzing the evolution of the resistance states that allow multilevel control. Indeed, analogue operation is a key point for achieving electronic neural synapses in neuromorphic systems, with synaptic weight information encoded in the different resistance states. This research has been carried out over a wide temperature range, between 40 and 340 K, as we are interested in testing the extent to which performance is maintained or modified, with a view to designing neuromorphic circuits that are also suitable in the low-temperature realm. We aim to prove that these simple, fast, high integration density structures can also be used in circuits designed for specific applications, such as aerospace systems.&#13;
 The RRAM devices studied in this work are TiN/Ti/8 nm-HfO2/TiN metal-insulator-metal (MIM) capacitors. Dielectric layers were atomic layer deposited (ALD). It has been demonstrated that the Ti coat in the top electrode acts as a scavenger that absorbs oxygen atoms from the HfO2 layer, and facilitates the creation of conductive filaments of oxygen vacancies [3]. In fact, the oxygen reservoir capability of Ti is well known, as it is able to attract and release oxygen atoms from or to the HfO2 layer during the RRAM operation [4]. The clustering of vacancies extends through the entire thickness of the oxide and, after an electroformig step, it joins the upper and lower electrodes and the device reaches the low resistance state (LRS). By applying adequate electrical signals, the filaments can be partially dissolved, which brings the device into the high-resistance state (HRS), with lower current values. The set process brings the device to the LRS state, while the reset one brings it to the HRS. The dependence of electrical conductivity on external applied electrical excitation allows triggering the device between the both states in a non-volatile manner [5].&#13;
 The experimental equipment used consisted of a Keithley 4200-SCS semiconductor parameter analyzer and a Lake Shore cryogenic probe station. Fig.1 shows current-voltage cycles measured at different temperatures; the averages values at each temperature, both in logarithmic and linear scale, are also shown. The functional window increases as temperature decreases.&#13;
 The evolutions of set and reset voltage values with temperature are depicted in Fig.2, whereas the current values (measured at 0.1 V) corresponding to the LRS and HRS can be seen in Fig.3. LRS resistance decreases as temperature increases, in agreement with semiconductor behaviour, probably due to a hopping conduction mechanism. Both set and reset voltages decrease as temperature increases; the reset process is smoother at high temperatures. The reduction in reset voltage variability as temperature increases is very notable.&#13;
 Finally, Fig. 4 shows a picture of the transient behaviour; in the right panel of the same figure, the amplitudes of the current transients in the reset state have been included in the external loop.&#13;
 To sum up, the resistive switching phenomena is studied in a wide temperature range. The LRS shows semiconducting behavior with temperature, most likely related to a hopping conduction mechanism. Switching voltages decrease as temperature increases, with a notable reduction in reset voltage variability. An excellent control of intermediate resistance state is shown through current transients at several voltages in the reset process.&#13;
 REFERENCES&#13;
 [1] M. Asif et al., Materials Today Electronics 1, 100004 (2022).&#13;
 [2] S. Slesazeck et al., Nanotechnology 30, 352003 (2019).&#13;
 [3] Z. Fang et al., IEEE Electron Device Letters 35, 9, 912-914 (2014).&#13;
 [4] H. Y. Lee et al., IEEE Electron Device Letters 31, 1, 44-46 (2010).&#13;
 [5] D. J. Wouters et al., Proceedings of the IEEE 103, 8, 1274-1288 (2015).&#13;
 &#13;
 &#13;
 &#13;
 &#13;
 Figure 1</abstract>
    <parentTitle language="eng">ECS Meeting Abstracts</parentTitle>
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Abstr."],"published-print":{"date-parts":[[2024,8,9]]},"abstract":"&lt;jats:p&gt;  \tOver the past decades, the demand for semiconductor memory devices has been steadily increasing, and is currently experiencing an unprecedented boost due to the development and expansion of artificial intelligence. Among emerging high-density non-volatile memories, resistive random-access memory (RRAM) is one of the best recourses for all kind of applications, such as neuromorphic computing or hardware security [1]. Although many materials have been evaluated for RRAM development, some of them with excellent results, HfO&lt;jats:sub&gt;2&lt;\/jats:sub&gt; is one of the established materials in CMOS domain due to its compatibility with standard materials and processes [2].&lt;\/jats:p&gt;\n               &lt;jats:p&gt;The main goal of this work is to study the switching capability and stability of HfO&lt;jats:sub&gt;2&lt;\/jats:sub&gt;-based RRAMs, as well as to explore their ability in the field of analogue applications, by analyzing the evolution of the resistance states that allow multilevel control. Indeed, analogue operation is a key point for achieving electronic neural synapses in neuromorphic systems, with synaptic weight information encoded in the different resistance states. This research has been carried out over a wide temperature range, between 40 and 340 K, as we are interested in testing the extent to which performance is maintained or modified, with a view to designing neuromorphic circuits that are also suitable in the low-temperature realm. We aim to prove that these simple, fast, high integration density structures can also be used in circuits designed for specific applications, such as aerospace systems.&lt;\/jats:p&gt;\n               &lt;jats:p&gt;The RRAM devices studied in this work are TiN\/Ti\/8 nm-HfO&lt;jats:sub&gt;2&lt;\/jats:sub&gt;\/TiN metal-insulator-metal (MIM) capacitors. Dielectric layers were atomic layer deposited (ALD). It has been demonstrated that the Ti coat in the top electrode acts as a scavenger that absorbs oxygen atoms from the HfO&lt;jats:sub&gt;2&lt;\/jats:sub&gt; layer, and facilitates the creation of conductive filaments of oxygen vacancies [3]. In fact, the oxygen reservoir capability of Ti is well known, as it is able to attract and release oxygen atoms from or to the HfO&lt;jats:sub&gt;2&lt;\/jats:sub&gt; layer during the RRAM operation [4]. The clustering of vacancies extends through the entire thickness of the oxide and, after an electroformig step, it joins the upper and lower electrodes and the device reaches the low resistance state (LRS). By applying adequate electrical signals, the filaments can be partially dissolved, which brings the device into the high-resistance state (HRS), with lower current values. The set process brings the device to the LRS state, while the reset one brings it to the HRS. The dependence of electrical conductivity on external applied electrical excitation allows triggering the device between the both states in a non-volatile manner [5].&lt;\/jats:p&gt;\n               &lt;jats:p&gt;The experimental equipment used consisted of a Keithley 4200-SCS semiconductor parameter analyzer and a Lake Shore cryogenic probe station. Fig.1 shows current-voltage cycles measured at different temperatures; the averages values at each temperature, both in logarithmic and linear scale, are also shown. The functional window increases as temperature decreases.&lt;\/jats:p&gt;\n               &lt;jats:p&gt;The evolutions of set and reset voltage values with temperature are depicted in Fig.2, whereas the current values (measured at 0.1 V) corresponding to the LRS and HRS can be seen in Fig.3. LRS resistance decreases as temperature increases, in agreement with semiconductor behaviour, probably due to a hopping conduction mechanism. Both set and reset voltages decrease as temperature increases; the reset process is smoother at high temperatures. The reduction in reset voltage variability as temperature increases is very notable.&lt;\/jats:p&gt;\n               &lt;jats:p&gt;Finally, Fig. 4 shows a picture of the transient behaviour; in the right panel of the same figure, the amplitudes of the current transients in the reset state have been included in the external loop.&lt;\/jats:p&gt;\n               &lt;jats:p&gt;To sum up, the resistive switching phenomena is studied in a wide temperature range. The LRS shows semiconducting behavior with temperature, most likely related to a hopping conduction mechanism. Switching voltages decrease as temperature increases, with a notable reduction in reset voltage variability. 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      <lastName>Wenger</lastName>
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      <firstName>Hector</firstName>
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      <firstName>Salvador</firstName>
      <lastName>Duenas</lastName>
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      <firstName>Helena</firstName>
      <lastName>Castan</lastName>
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      <firstName>Ignacio</firstName>
      <lastName>Iñiguez de la Torre</lastName>
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    <author>
      <firstName>Tomas</firstName>
      <lastName>Gonzalez</lastName>
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      <firstName>Keerthi</firstName>
      <lastName>Dorai Swamy Reddy</lastName>
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      <firstName>Max</firstName>
      <lastName>Uhlmann</lastName>
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      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
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    <author>
      <firstName>Eduardo</firstName>
      <lastName>Perez</lastName>
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    <subject>
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      <value>RRAM</value>
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    <title language="eng">Fast circuit simulation of memristive crossbar arrays with bimodal stochastic synaptic weights</title>
    <abstract language="eng">This paper presents an approach for highly efficient circuit simulation of hardware-based artificial neural networks by using memristive crossbar array architectures. There are already possibilities to test neural networks with stochastic weights via simulations like the macro model NeuroSim. However, the noise-based variability approach offers more realistic setting options including elements of a classical circuit simulation for more precise analysis of neural networks. With this approach, statistical parameter fluctuations can be simulated based on different distribution functions of devices. In Cadence Virtuoso, a simulation of a crossbar array with 10 synaptic weights following a bimodal distribution, the new approach shows a 1,000x speedup compared to a Monte Carlo simulation. Initial tests of a memristive crossbar array with over 15,000 stochastic weights to classify the MNIST dataset show that the new approach can be used to test the functionality of hardware-based neural networks.</abstract>
    <parentTitle language="eng">2024 IEEE Latin American Electron Devices Conference (LAEDC)</parentTitle>
    <identifier type="doi">10.1109/LAEDC61552.2024.10555829</identifier>
    <identifier type="issn">979-8-3503-6129-2</identifier>
    <identifier type="isbn">979-8-3503-6130-8</identifier>
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    <title language="eng">Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator</title>
    <abstract language="eng">The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 % and 18 %, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero.</abstract>
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    <title language="eng">Kinetic Monte Carlo simulation analysis of the conductance drift in Multilevel HfO2-based RRAM devices</title>
    <abstract language="eng">The drift characteristics of valence change memory (VCM) devices have been analyzed through both experimental analysis and 3D kinetic Monte Carlo (kMC) simulations.</abstract>
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    <title language="eng">A compact one-transistor-multiple-RRAM characterization platform</title>
    <abstract language="eng">Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP’s 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 %. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.</abstract>
    <parentTitle language="eng">IEEE transactions on circuits and systems I : regular papers</parentTitle>
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    <author>
      <firstName>Max</firstName>
      <lastName>Uhlmann</lastName>
    </author>
    <submitter>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </submitter>
    <author>
      <firstName>Milosz</firstName>
      <lastName>Krysik</lastName>
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    <author>
      <firstName>Jianan</firstName>
      <lastName>Wen</lastName>
    </author>
    <author>
      <firstName>Max</firstName>
      <lastName>Frohberg</lastName>
    </author>
    <author>
      <firstName>Andrea</firstName>
      <lastName>Baroni</lastName>
    </author>
    <author>
      <firstName>Keerthi Dorai Swamy</firstName>
      <lastName>Reddy</lastName>
    </author>
    <author>
      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
    </author>
    <author>
      <firstName>Philip</firstName>
      <lastName>Ostrovskyy</lastName>
    </author>
    <author>
      <firstName>Krzysztof</firstName>
      <lastName>Piotrowski</lastName>
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    <author>
      <firstName>Corrado</firstName>
      <lastName>Carta</lastName>
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    <author>
      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
    </author>
    <author>
      <firstName>Gerhard</firstName>
      <lastName>Kahmen</lastName>
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    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
    </subject>
    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>Vector Matrix Multiplication</value>
    </subject>
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    <pageNumber>14</pageNumber>
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    <publisherPlace>Piscataway, NJ</publisherPlace>
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    <completedDate>2025-12-02</completedDate>
    <publishedDate>--</publishedDate>
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    <title language="eng">ReFFT : an energy-efficient RRAM-based FFT accelerator</title>
    <abstract language="eng">The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector–matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks.</abstract>
    <parentTitle language="eng">IEEE transactions on computer-aided design of integrated circuits and systems</parentTitle>
    <identifier type="doi">10.1109/TCAD.2025.3627146</identifier>
    <identifier type="issn">0278-0070</identifier>
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    <author>
      <firstName>Jianan</firstName>
      <lastName>Wen</lastName>
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      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
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      <firstName>Andrea</firstName>
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      <language>eng</language>
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      <value>Accelerator</value>
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