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    <title language="eng">Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance</title>
    <abstract language="eng">Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of HfO2   dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm HfO2   dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology.</abstract>
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      <firstName>Christian</firstName>
      <lastName>Wenger</lastName>
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    <author>
      <firstName>Eduardo</firstName>
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      <firstName>Andrea</firstName>
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      <firstName>Mamathamba Kalishettyhalli</firstName>
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      <firstName>Steffen</firstName>
      <lastName>Marschmeyer</lastName>
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      <lastName>Wenger</lastName>
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      <firstName>Andreas</firstName>
      <lastName>Mai</lastName>
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    <subject>
      <language>eng</language>
      <type>uncontrolled</type>
      <value>RRAM</value>
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    <collection role="institutes" number="1521">FG Halbleitermaterialien</collection>
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    <completedDate>2024-10-29</completedDate>
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    <title language="eng">A flexible and fast digital twin for RRAM systems applied for training resilient neural networks</title>
    <abstract language="eng">Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).</abstract>
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      <firstName>Daniel</firstName>
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      <firstName>Ankit</firstName>
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      <firstName>Tim</firstName>
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      <firstName>Christian</firstName>
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      <value>Neural network</value>
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    <title language="eng">Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator</title>
    <abstract language="eng">The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 % and 18 %, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero.</abstract>
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    <title language="eng">Kinetic Monte Carlo simulation analysis of the conductance drift in Multilevel HfO2-based RRAM devices</title>
    <abstract language="eng">The drift characteristics of valence change memory (VCM) devices have been analyzed through both experimental analysis and 3D kinetic Monte Carlo (kMC) simulations.</abstract>
    <parentTitle language="eng">Nanoscale</parentTitle>
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      <lastName>Roldán</lastName>
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      <firstName>Eduardo</firstName>
      <lastName>Pérez</lastName>
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    <title language="eng">A compact one-transistor-multiple-RRAM characterization platform</title>
    <abstract language="eng">Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP’s 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 %. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.</abstract>
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      <firstName>Milosz</firstName>
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      <firstName>Jianan</firstName>
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      <firstName>Andrea</firstName>
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      <firstName>Eduardo</firstName>
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      <firstName>Gerhard</firstName>
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      <value>RRAM</value>
    </subject>
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      <language>eng</language>
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    <title language="eng">ReFFT : an energy-efficient RRAM-based FFT accelerator</title>
    <abstract language="eng">The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector–matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks.</abstract>
    <parentTitle language="eng">IEEE transactions on computer-aided design of integrated circuits and systems</parentTitle>
    <identifier type="doi">10.1109/TCAD.2025.3627146</identifier>
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