@misc{WenBaroniPerezetal., author = {Wen, Jianan and Baroni, Andrea and Perez, Eduardo and Ulbricht, Markus and Wenger, Christian and Krstic, Milos}, title = {Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages}, series = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, journal = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, isbn = {978-1-6654-5938-9}, issn = {2765-933X}, doi = {10.1109/DFT56152.2022.9962345}, pages = {1 -- 6}, abstract = {RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states.}, language = {en} } @misc{BuschekMantheyEckhardetal., author = {Buschek, Johannes and Manthey, Kristian and Eckhard, Andreas and Reulke, Ralf}, title = {In-Orbit Real-Time CMOS TDI Detector Validation and Control to Meet Constant Imaging Quality Over the Mission Life Time}, series = {SPIE 12232, Earth Observing Systems XXVII, 1223205 (30 September 2022)}, journal = {SPIE 12232, Earth Observing Systems XXVII, 1223205 (30 September 2022)}, doi = {10.1117/12.2631978}, language = {en} } @misc{SuetbasKahmen, author = {S{\"u}tbas, Batuhan and Kahmen, Gerhard}, title = {A 7.2-mW V-Band Frequency Doubler with 14\% Total Efficiency in 130-nm SiGe BiCMOS}, series = {IEEE Microwave and Wireless Components Letters}, volume = {32}, journal = {IEEE Microwave and Wireless Components Letters}, number = {6}, issn = {1531-1309}, doi = {10.1109/LMWC.2022.3141557}, pages = {579 -- 582}, language = {en} } @misc{AkhtarDabrowskiLukoseetal., author = {Akhtar, Fatima and Dabrowski, Jaroslaw and Lukose, Rasuole and Wenger, Christian and Lukosius, Mindaugas}, title = {Chemical Vapor Deposition Growth of Graphene on 200 mm Ge (110)/Si Wafers and Ab Initio Analysis of Differences in Growth Mechanisms on Ge (110) and Ge (001)}, series = {ACS Applied Materials \& Interfaces}, volume = {15}, journal = {ACS Applied Materials \& Interfaces}, number = {30}, issn = {1944-8244}, doi = {10.1021/acsami.3c05860}, pages = {36966 -- 36974}, abstract = {For the fabrication of modern graphene devices, uniform growth of high-quality monolayer graphene on wafer scale is important. This work reports on the growth of large-scale graphene on semiconducting 8 inch Ge(110)/Si wafers by chemical vapor deposition and a DFT analysis of the growth process. Good graphene quality is indicated by the small FWHM (32 cm-1) of the Raman 2D band, low intensity ratio of the Raman D and G bands (0.06), and homogeneous SEM images and is confirmed by Hall measurements: high mobility (2700 cm2/Vs) and low sheet resistance (800 Ω/sq). In contrast to Ge(001), Ge(110) does not undergo faceting during the growth. We argue that Ge(001) roughens as a result of vacancy accumulation at pinned steps, easy motion of bonded graphene edges across (107) facets, and low energy cost to expand Ge area by surface vicinals, but on Ge(110), these mechanisms do not work due to different surface geometries and complex reconstruction.}, language = {en} } @misc{DerschPerezBoschQuesadaPerezetal., author = {Dersch, Nadine and Perez-Bosch Quesada, Emilio and Perez, Eduardo and Wenger, Christian and Roemer, Christian and Schwarz, Mike and Kloes, Alexander}, title = {Efficient circuit simulation of a memristive crossbar array with synaptic weight variability}, series = {Solid State Electronics}, volume = {209}, journal = {Solid State Electronics}, issn = {0038-1101}, doi = {10.1016/j.sse.2023.108760}, abstract = {In this paper, we present a method for highly-efficient circuit simulation of a hardware-based artificial neural network realized in a memristive crossbar array. The statistical variability of the devices is considered by a noise-based simulation technique. For the simulation of a crossbar array with 8 synaptic weights in Cadence Virtuoso the new approach shows a more than 200x speed improvement compared to a Monte Carlo approach, yielding the same results. In addition, first results of an ANN with more than 15,000 memristive devices classifying test data of the MNIST dataset are shown, for which the speed improvement is expected to be several orders of magnitude. Furthermore, the influence on the classification of parasitic resistances of the connection lines in the crossbar is shown.}, language = {en} } @misc{RizziBaroniGlukhovetal., author = {Rizzi, Tommaso and Baroni, Andrea and Glukhov, Artem and Bertozzi, Davide and Wenger, Christian and Ielmini, Daniele and Zambelli, Cristian}, title = {Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAs}, series = {IEEE Transactions on Device and Materials Reliability}, volume = {23}, journal = {IEEE Transactions on Device and Materials Reliability}, number = {3}, issn = {1530-4388}, doi = {10.1109/TDMR.2023.3259015}, pages = {328 -- 336}, abstract = {Resistive Random Access Memory (RRAM) technology holds promises to improve the Field Programmable Gate Array (FPGA) performance, reduce the area footprint, and dramatically lower run-time energy requirements compared to the state-of-the-art CMOS-based products. However, the integration of RRAM in FPGAs is hindered by the high programming power consumption and by non-ideal behaviors of the device due to its stochastic nature that may overshadow the benefits in normal operation mode. To cope with these challenges, optimized programming strategies have to be investigated. In this work, we explore the impact that different procedures to set the device have on the run-time performance. Process, voltage, and temperature (PVT) variations as well as time-dependent drift effect of the RRAM device are considered in the assessment of 4T1R MUX designs characteristics. The comparison with tradition CMOS implementations reveals how the choice of the target resistive state and the programming algorithm are key design aspects to reduce the run-time delay and energy metrics, while at the same time improving the robustness against the different sources of variations.}, language = {en} } @misc{PerezMaldonadoMahadevaiahetal., author = {Perez, Eduardo and Maldonado, David and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Cantudo, Antonio and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {A comparison of resistive switching parameters for memristive devices with HfO2 monolayers and Al2O3/HfO2 bilayers at the wafer scale}, series = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, journal = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0240-0}, doi = {10.1109/CDE58627.2023.10339417}, pages = {5}, abstract = {Memristive devices integrated in 200 mm wafers manufactured in 130 nm CMOS technology with two different dielectrics, namely, a HfO2 monolayer and an Al2O3/HfO2 bilayer, have been measured. The cycle-to-cycle (C2C) and device-todevice (D2D) variability have been analyzed at the wafer scale using different numerical methods to extract the set (Vset) and reset (Vreset) voltages. Some interesting differences between both technologies were found in terms of switching characteristics}, language = {en} } @misc{CapistaLukoseMajnoonetal., author = {Capista, Daniele and Lukose, Rasuole and Majnoon, Farnaz and Lisker, Marco and Wenger, Christian and Lukosius, Mindaugas}, title = {Study on the metal -graphene contact resistance achieved with one -dimensional contact architecture}, series = {IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), Paestum, Italy, 22-25 October 2023}, journal = {IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), Paestum, Italy, 22-25 October 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-3546-0}, doi = {10.1109/NMDC57951.2023.10343775}, pages = {118 -- 119}, abstract = {Graphene has always been considered as one of the materials with the greatest potential for the realization of improved microelectronic and photonic devices. But to actually reach its full potential in Si CMOS technology, graphene -based devices need to overcome different challenges. They do not only need to have better performances than standard devices, but they also need to be compatible with the production of standard Si based devices. To address the first challenge the main route requires the optimization of the contact resistance, that highly reduces the devices performance, while the second challenges requires the integration of graphene inside the standard production lines used for microelectronic. In this work we used an 8" wafer pilot -line to realize our devices and we studied the behavior of the contact resistance between metal and graphene obtained by one -dimensional contact architecture between the two materials. The contact resistance has been measured by means of Transmission Line Method (TLM) with several contact patterning.}, language = {en} } @misc{LukosiusLukoseLiskeretal., author = {Lukosius, Mindaugas and Lukose, Rasuolė and Lisker, Marco and Dubey, P. K. and Raju, A. I. and Capista, Daniele and Majnoon, Farnaz and Mai, A. and Wenger, Christian}, title = {Developments of Graphene devices in 200 mm CMOS pilot line}, series = {Proc. Nanotechnology Materials and Devices Conference (NMDC 2023),Paestum, Italy, 22-25 October 2023}, journal = {Proc. Nanotechnology Materials and Devices Conference (NMDC 2023),Paestum, Italy, 22-25 October 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-3546-0}, doi = {10.1109/NMDC57951.2023.10343569}, pages = {505 -- 506}, abstract = {Due to the unique electronic band structure, graphene has opened great potential to extend the functionality of a large variety of devices. Despite the significant progress in the fabrication of various graphene based microelectronic devices, the integration of graphene devices still lack the stability and compatibility with Si-technology processes. Therefore, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance. This study aims to explore various aspects of graphene research on a 200mm pilot line, with a focus on simulations and fabrication of graphene modulator. To be more precise, it includes design and fabrication of the layouts, necessary mask sets, creation of the flows, fabrication, and measurements of the Gr modulators on 200 mm wafers.}, language = {en} } @misc{MaldonadoCantudoPerezetal., author = {Maldonado, David and Cantudo, Antonio and Perez, Eduardo and Romero-Zaliz, Rocio and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance}, series = {Frontiers in Neuroscience}, volume = {17}, journal = {Frontiers in Neuroscience}, issn = {1662-4548}, doi = {10.3389/fnins.2023.1271956}, abstract = {We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics.}, language = {en} } @misc{PerezMahadevaiahPerezBoschQuesadaetal., author = {Perez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Wenger, Christian}, title = {In-depth characterization of switching dynamics in amorphous HfO2 memristive arrays for the implementation of synaptic updating rules}, series = {Japanese Journal of Applied Physics}, volume = {61}, journal = {Japanese Journal of Applied Physics}, issn = {0021-4922}, doi = {10.35848/1347-4065/ac6a3b}, pages = {1 -- 7}, abstract = {Accomplishing truly analog conductance modulation in memristive arrays is crucial in order to implement the synaptic plasticity in hardware-based neuromorphic systems. In this paper, such a feature was addressed by exploiting the inherent stochasticity of switching dynamics in amorphous HfO2 technology. A thorough statistical analysis of experimental characteristics measured in 4 kbit arrays by using trains of identical depression/potentiation pulses with different voltage amplitudes and pulse widths provided the key to develop two different updating rules and to define their optimal programming parameters. The first rule is based on applying a specific number of identical pulses until the conductance value achieves the desired level. The second one utilized only one single pulse with a particular amplitude to achieve the targeted conductance level. In addition, all the results provided by the statistical analysis performed may play an important role in understanding better the switching behavior of this particular technology.}, language = {en} } @misc{DziallasFatemiPeczeketal., author = {Dziallas, Giannino and Fatemi, Adel and Peczek, Anna and Zimmermann, Lars and Malignaggi, Andrea and Kahmen, Gerhard}, title = {A 56-Gb/s Optical Receiver with 2.08-µA Noise Monolithically Integrated into a 250-nm SiGe BiCMOS Technology}, series = {IEEE Transactions on Microwave Theory and Techniques}, volume = {70}, journal = {IEEE Transactions on Microwave Theory and Techniques}, number = {1}, issn = {0018-9480}, doi = {10.1109/TMTT.2021.3104838}, pages = {10}, language = {en} } @misc{IseiniMalignaggiKorndoerferetal., author = {Iseini, Festim and Malignaggi, Andrea and Kornd{\"o}rfer, Falk and Inac, Mesut and Kahmen, Gerhard}, title = {Lumped Ultra-Broadband Linear Driver in 130 nm SiGe SG13G3 Technology}, series = {IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)}, journal = {IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)}, doi = {10.1109/BCICTS53451.2022.10051703}, pages = {4}, language = {en} } @misc{Kahmen, author = {Kahmen, Gerhard}, title = {SiGe BiCMOS as Enabling Technology for Next Generation RF \& THz Systems}, series = {EuMIC 2021 Abstract Cards, 16th European Microwave Integrated Circuits Conference (EuMIC), London, United Kingdom, 2022}, journal = {EuMIC 2021 Abstract Cards, 16th European Microwave Integrated Circuits Conference (EuMIC), London, United Kingdom, 2022}, publisher = {IEEE}, address = {Piscataway, NJ}, doi = {10.23919/EuMIC50153.2022.9783893}, pages = {S. 21}, language = {en} } @misc{StrobelAlvaradoChavarinKnautetal., author = {Strobel, Carsten and Alvarado Chavarin, Carlos and Knaut, Martin and V{\"o}lkel, Sandra and Albert, Matthias and Hiess, Andre and Max, Benjamin and Wenger, Christian and Kirchner, Robert and Mikolajick, Thomas}, title = {High Gain Graphene Based Hot Electron Transistor with Record High Saturated Output Current Density}, series = {Advanced Electronic Materials}, volume = {10}, journal = {Advanced Electronic Materials}, number = {2}, issn = {2199-160X}, doi = {10.1002/aelm.202300624}, abstract = {Hot electron transistors (HETs) represent an exciting frontier in semiconductor technology, holding the promise of high-speed and high-frequency electronics. With the exploration of two-dimensional materials such as graphene and new device architectures, HETs are poised to revolutionize the landscape of modern electronics. This study highlights a novel HET structure with a record output current density of 800 A/cm² and a high current gain α, fabricated using a scalable fabrication approach. The HET structure comprises two-dimensional hexagonal boron nitride (hBN) and graphene layers wet transferred to a germanium substrate. The combination of these materials results in exceptional performance, particularly in terms of the highly saturated output current density. The scalable fabrication scheme used to produce the HET opens up opportunities for large-scale manufacturing. This breakthrough in HET technology holds promise for advanced electronic applications, offering high current capabilities in a practical and manufacturable device.}, language = {en} } @misc{PechmannPerezWengeretal., author = {Pechmann, Stefan and Perez, Eduardo and Wenger, Christian and Hagelauer, Amelie}, title = {A current mirror Based read circuit design with multi-level capability for resistive switching deviceb}, series = {2024 International Conference on Electronics, Information, and Communication (ICEIC)}, journal = {2024 International Conference on Electronics, Information, and Communication (ICEIC)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-7188-8}, issn = {2767-7699}, doi = {10.1109/ICEIC61013.2024.10457188}, pages = {4}, abstract = {This paper presents a read circuit design for resistive memory cells based on current mirrors. The circuit utilizes high-precision current mirrors and reference cells to determine the state of resistive memory using comparators. It offers a high degree in adaptability in terms of both resistance range and number of levels. Special emphasis was put on device protection to prevent accidental programming of the memory during read operations. The realized circuit can resolve eight states with a resolution of up to 1 k Ω, realizing a digitization of the analog memory information. Furthermore, the integration in a complete memory macro is shown. The circuit was realized in a 130 nm-process but can easily be adapted to other processes and resistive memory technologies.}, language = {en} } @misc{NikiruyPerezBaronietal., author = {Nikiruy, Kristina and Perez, Eduardo and Baroni, Andrea and Reddy, Keerthi Dorai Swamy and Pechmann, Stefan and Wenger, Christian and Ziegler, Martin}, title = {Blooming and pruning: learning from mistakes with memristive synapses}, series = {Scientific Reports}, volume = {14}, journal = {Scientific Reports}, number = {1}, issn = {2045-2322}, doi = {10.1038/s41598-024-57660-4}, abstract = {AbstractBlooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. This approach provides hardware, local, and energy-efficient learning. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks.}, language = {en} } @misc{StrobelAlvaradoChavarinLeszczynskietal., author = {Strobel, Carsten and Alvarado Chavarin, Carlos and Leszczynski, Sebastian and Richter, Karola and Knaut, Martin and Reif, Johanna and V{\"o}lkel, Sandra and Albert, Matthias and Wenger, Christian and Bartha, Johann Wolfgang and Mikolajick, Thomas}, title = {Improved Graphene-base Heterojunction Transistor with Different Collector Semi-conductors for High-frequency Applications}, series = {Advanced Materials Letters}, volume = {13}, journal = {Advanced Materials Letters}, number = {1}, issn = {0976-3961}, doi = {10.5185/amlett.2022.011688}, abstract = {A new kind of transistor device with a graphene monolayer embedded between two n-type silicon layers is fabricated and characterized. The device is called graphene-base heterojunction transistor (GBHT). The base-voltage controls the current of the device flowing from the emitter via graphene to the collector. The transit time for electrons passing by the ultrathin graphene layer is extremely short which makes the device very promising for high frequency RF-electronics. The output current of the device is saturated and clearly modulated by the base voltage. Further, the silicon collector of the GBHT is replaced by germanium to improve the device performance. This enabled the collector current to be increased by almost three orders of magnitude. Also, the common-emitter current gain (Ic/Ib) increased from 10-3 to approximately 0.3 for the newly designed device. However, the ON-OFF ratio of the improved germanium based GBHT has so far been rather low. Further optimizations are necessary in order to fully exploit the potential of the graphene-base heterojunction transistor.}, language = {en} } @misc{KloesBischoffLeiseetal., author = {Kloes, Alexander and Bischoff, Carl and Leise, Jakob and Perez-Bosch Quesada, Emilio and Wenger, Christian and Perez, Eduardo}, title = {Stochastic switching of memristors and consideration in circuit simulation}, series = {Solid State Electronics}, volume = {201}, journal = {Solid State Electronics}, issn = {0038-1101}, doi = {10.1016/j.sse.2023.108606}, abstract = {We explore the stochastic switching of oxide-based memristive devices by using the Stanford model for circuit simulation. From measurements, the device-to-device (D2D) and cycle-to-cycle (C2C) statistical variation is extracted. In the low-resistive state (LRS) dispersion by D2D variability is dominant. In the high-resistive state (HRS) C2C dispersion becomes the main source of fluctuation. A statistical procedure for the extraction of parameters of the compact model is presented. Thereby, in a circuit simulation the typical D2D and C2C fluctuations of the current-voltage (I-V) characteristics can be emulated by extracting statistical parameters of key model parameters. The statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of memory cells or can be used to emulate the synaptic behavior of these devices in artificial neural networks realized by a crossbar array of memristors.}, language = {en} } @misc{PrueferWengerBieretal., author = {Pr{\"u}fer, Mareike and Wenger, Christian and Bier, Frank F. and Laux, Eva-Maria and H{\"o}lzel, Ralph}, title = {Activity of AC electrokinetically immobilized horseradish peroxidase}, series = {Electrophoresis}, volume = {43}, journal = {Electrophoresis}, number = {18-19}, issn = {1522-2683}, doi = {10.1002/elps.202200073}, pages = {1920 -- 1933}, abstract = {Dielectrophoresis(DEP) is an AC electrokinetic effect mainly used to manipulate cells.Smaller particles,like virions,antibodies,enzymes,andevendyemolecules can be immobilized by DEP as well. In principle, it was shown that enzymesare active after immobilization by DEP, but no quantification of the retainedactivity was reported so far. In this study, the activity of the enzyme horseradishperoxidase (HRP) is quantified after immobilization by DEP. For this, HRP is immobilized on regular arrays of titanium nitride ring electrodes of 500 nm diameter and 20 nm widths. The activity of HRP on the electrode chip is measured with a limit of detection of 60 fg HRP by observing the enzymatic turnover of Amplex Red and H2O2 to fluorescent resoruf in by fluorescence microscopy. The initial activity of the permanently immobilized HRP equals up to 45\% of the activity that can be expected for an ideal monolayer of HRP molecules on all electrodes of the array. Localization of the immobilizate on the electrodesis accomplished by staining with the fluorescent product of the enzyme reac-tion.The high residual activity of enzymes after AC field induced immobilization shows the method's suitability for biosensing and research applications.}, language = {en} }