@misc{SoltaniZarrinZahariMahadevaiahetal., author = {Soltani Zarrin, Pouya and Zahari, Finn and Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez, Eduardo and Kohlstedt, Hermann and Wenger, Christian}, title = {Neuromorphic on‑chip recognition of saliva samples of COPD and healthy controls using memristive devices}, series = {Scientific Reports}, volume = {10}, journal = {Scientific Reports}, issn = {2045-2322}, doi = {10.1038/s41598-020-76823-7}, abstract = {Chronic Obstructive Pulmonary Disease (COPD) is a life-threatening lung disease, affecting millions of people worldwide. Implementation of Machine Learning (ML) techniques is crucial for the effective management of COPD in home-care environments. However, shortcomings of cloud-based ML tools in terms of data safety and energy efficiency limit their integration with low-power medical devices. To address this, energy efficient neuromorphic platforms can be used for the hardware-based implementation of ML methods. Therefore, a memristive neuromorphic platform is presented in this paper for the on-chip recognition of saliva samples of COPD patients and healthy controls. The results of its performance evaluations showed that the digital neuromorphic chip is capable of recognizing unseen COPD samples with accuracy and sensitivity values of 89\% and 86\%, respectively. Integration of this technology into personalized healthcare devices will enable the better management of chronic diseases such as COPD.}, language = {en} } @misc{ZahariPerezMahadevaiahetal., author = {Zahari, Finn and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Kohlstedt, Hermann and Wenger, Christian and Ziegler, Martin}, title = {Analogue pattern recognition with stochastic switching binary CMOS‑integrated memristive devices}, series = {Scientific Reports}, volume = {10}, journal = {Scientific Reports}, issn = {2045-2322}, doi = {10.1038/s41598-020-71334-x}, pages = {15}, abstract = {Biological neural networks outperform todays computer technology in terms of power consumption and computing speed when associative tasks, like pattern recognition, are to be solved. The analogue and massive parallel in-memory computing in biology differs strongly with conventional transistor electronics using the von Neumann architecture. Therefore, novel bio-inspired computing architectures are recently highly investigated in the area of neuromorphic computing. Here, memristive devices, which serve as non-volatile resistive memory, are used to emulate the plastic behaviour of biological synapses. In particular, CMOS integrated resistive random access memory (RRAM) devices are promising candidates to extend conventional CMOS technology in neuromorphic systems. However, dealing with the inherent stochasticity of the resistive switching effect can be challenging for network performance. In this work, the probabilistic switching is exploited to emulate stochastic plasticity with fully CMOS integrated binary RRAM devices. Two different RRAM technologies with different device variabilities are investigated in detail and their use in a stochastic artificial neural network (StochANN) to solve the MINST pattern recognition task is examined. A mixed-signal implementation with hardware synapses and software neurons as well as numerical simulations show the proposed concept of stochastic computing is able to handle analogue data with binary memory cells.}, language = {en} } @misc{PerezBoschQuesadaPerezMahadevaiahetal., author = {Perez-Bosch Quesada, Emilio and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Wenger, Christian}, title = {Memristive-based in-memory computing: from device to large-scale CMOS integration}, series = {Neuromorphic Computing and Engineering}, volume = {1}, journal = {Neuromorphic Computing and Engineering}, number = {2}, issn = {2634-4386}, doi = {10.1088/2634-4386/ac2cd4}, pages = {8}, abstract = {With the rapid emergence of in-memory computing systems based on memristive technology, the integration of such memory devices in large-scale architectures is one of the main aspects to tackle. In this work we present a study of HfO2-based memristive devices for their integration in large-scale CMOS systems, namely 200 mm wafers. The DC characteristics of single metal-insulator-metal devices are analyzed taking under consideration device-to-device variabilities and switching properties. Furthermore, the distribution of the leakage current levels in the pristine state of the samples are analyzed and correlated to the amount of formingless memristors found among the measured devices. Finally, the obtained results are fitted into a physic-based compact model that enables their integration into larger-scale simulation environments.}, language = {en} } @misc{RomeroZalizCantudoPerezetal., author = {Romero-Zaliz, Rocio and Cantudo, Antonio and P{\´e}rez, Eduardo and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {An Analysis on the Architecture and the Size of Quantized Hardware Neural Networks Based on Memristors}, series = {Electronics (MDPI)}, volume = {10}, journal = {Electronics (MDPI)}, number = {24}, issn = {2079-9292}, doi = {10.3390/electronics10243141}, abstract = {We have performed different simulation experiments in relation to hardware neural networks (NN) to analyze the role of the number of synapses for different NN architectures in the network accuracy, considering different datasets. A technology that stands upon 4-kbit 1T1R ReRAM arrays, where resistive switching devices based on HfO2 dielectrics are employed, is taken as a reference. In our study, fully dense (FdNN) and convolutional neural networks (CNN) were considered, where the NN size in terms of the number of synapses and of hidden layer neurons were varied. CNNs work better when the number of synapses to be used is limited. If quantized synaptic weights are included, we observed thatNNaccuracy decreases significantly as the number of synapses is reduced; in this respect, a trade-off between the number of synapses and the NN accuracy has to be achieved. Consequently, the CNN architecture must be carefully designed; in particular, it was noticed that different datasets need specific architectures according to their complexity to achieve good results. It was shown that due to the number of variables that can be changed in the optimization of a NN hardware implementation, a specific solution has to be worked in each case in terms of synaptic weight levels, NN architecture, etc.}, language = {en} } @misc{FritscherKnoedtelMallahetal., author = {Fritscher, Markus and Kn{\"o}dtel, Johannes and Mallah, Maen and Pechmann, Stefan and Perez-Bosch Quesada, Emilio and Rizzi, Tommaso and Wenger, Christian and Reichenbach, Marc}, title = {Mitigating the Effects of RRAM Process Variation on the Accuracy of Artifical Neural Networks}, series = {Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science}, journal = {Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science}, publisher = {Springer}, isbn = {978-3-031-04579-0}, issn = {0302-9743}, doi = {10.1007/978-3-031-04580-6_27}, pages = {401 -- 417}, abstract = {Weight storage is a key challenge in the efficient implementation of artificial neural networks. Novel memory technologies such as RRAM are able to greatly improve density and introduce non-volatility and multibit capabilities to this component of ANN accelerators. The usage of RRAM in this domain comes with downsides, mainly caused by cycle-to-cycle and device-to-device variability leading to erroneous readouts, greatly affecting digital systems. ANNs have the ability to compensate for this by their inherent redundancy and usually exhibit a gradual deterioration in the accuracy of the task at hand. This means, that slight error rates can be acceptable for weight storage in an ANN accelerator. In this work we link device-to-device variability to the accuracy of an ANN for such an accelerator. From this study, we can estimate how strongly a certain net is affected by a certain device parameter variability. This methodology is then used to present three mitigation strategies and to evaluate how they affect the reaction of the network to variability: a) Dropout Layers b) Fault-Aware Training c) Redundancy. These mitigations are then evaluated by their ability to improve accuracy and to lower hardware overhead by providing data for a real-word example. We improved this network's resilience in such a way that it could tolerate double the variation in one of the device parameters (standard deviation of the oxide thickness can be 0.4 nm instead of 0.2 nm while maintaining sufficient accuracy.)}, language = {en} } @misc{PerezMahadevaiahPerezBoschQuesadaetal., author = {P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Wenger, Christian}, title = {In-depth characterization of switching dynamics in amorphous HfO2 memristive arrays for the implementation of synaptic updating rules}, series = {Japanese Journal of Applied Physics}, volume = {61}, journal = {Japanese Journal of Applied Physics}, issn = {0021-4922}, doi = {10.35848/1347-4065/ac6a3b}, pages = {1 -- 7}, abstract = {Accomplishing truly analog conductance modulation in memristive arrays is crucial in order to implement the synaptic plasticity in hardware-based neuromorphic systems. In this paper, such a feature was addressed by exploiting the inherent stochasticity of switching dynamics in amorphous HfO2 technology. A thorough statistical analysis of experimental characteristics measured in 4 kbit arrays by using trains of identical depression/potentiation pulses with different voltage amplitudes and pulse widths provided the key to develop two different updating rules and to define their optimal programming parameters. The first rule is based on applying a specific number of identical pulses until the conductance value achieves the desired level. The second one utilized only one single pulse with a particular amplitude to achieve the targeted conductance level. In addition, all the results provided by the statistical analysis performed may play an important role in understanding better the switching behavior of this particular technology.}, language = {en} } @misc{PerezMaldonadoPerezBoschQuesadaetal., author = {P{\´e}rez, Eduardo and Maldonado, David and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Jimenez-Molinos, Francisco and Wenger, Christian}, title = {Parameter Extraction Methods for Assessing Device-to-Device and Cycle-to-Cycle Variability of Memristive Devices at Wafer Scale}, series = {IEEE Transactions on Electron Devices}, volume = {70}, journal = {IEEE Transactions on Electron Devices}, number = {1}, issn = {0018-9383}, doi = {10.1109/TED.2022.3224886}, pages = {360 -- 365}, abstract = {The stochastic nature of the resistive switching (RS) process in memristive devices makes device-to-device (DTD) and cycle-to-cycle (CTC) variabilities relevant magnitudes to be quantified and modeled. To accomplish this aim, robust and reliable parameter extraction methods must be employed. In this work, four different extraction methods were used at the production level (over all the 108 devices integrated on 200-mm wafers manufactured in the IHP 130-nm CMOS technology) in order to obtain the corresponding collection of forming, reset, and set switching voltages. The statistical analysis of the experimental data (mean and standard deviation (SD) values) was plotted by using heat maps, which provide a good summary of the whole data at a glance and, in addition, an easy manner to detect inhomogeneities in the fabrication process.}, language = {en} } @misc{PechmannPerezWengeretal., author = {Pechmann, Stefan and P{\´e}rez, Eduardo and Wenger, Christian and Hagelauer, Amelie}, title = {A current mirror Based read circuit design with multi-level capability for resistive switching deviceb}, series = {2024 International Conference on Electronics, Information, and Communication (ICEIC)}, journal = {2024 International Conference on Electronics, Information, and Communication (ICEIC)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-7188-8}, issn = {2767-7699}, doi = {10.1109/ICEIC61013.2024.10457188}, pages = {4}, abstract = {This paper presents a read circuit design for resistive memory cells based on current mirrors. The circuit utilizes high-precision current mirrors and reference cells to determine the state of resistive memory using comparators. It offers a high degree in adaptability in terms of both resistance range and number of levels. Special emphasis was put on device protection to prevent accidental programming of the memory during read operations. The realized circuit can resolve eight states with a resolution of up to 1 k Ω, realizing a digitization of the analog memory information. Furthermore, the integration in a complete memory macro is shown. The circuit was realized in a 130 nm-process but can easily be adapted to other processes and resistive memory technologies.}, language = {en} } @misc{KloesBischoffLeiseetal., author = {Kloes, Alexander and Bischoff, Carl and Leise, Jakob and Perez-Bosch Quesada, Emilio and Wenger, Christian and P{\´e}rez, Eduardo}, title = {Stochastic switching of memristors and consideration in circuit simulation}, series = {Solid State Electronics}, volume = {201}, journal = {Solid State Electronics}, issn = {0038-1101}, doi = {10.1016/j.sse.2023.108606}, abstract = {We explore the stochastic switching of oxide-based memristive devices by using the Stanford model for circuit simulation. From measurements, the device-to-device (D2D) and cycle-to-cycle (C2C) statistical variation is extracted. In the low-resistive state (LRS) dispersion by D2D variability is dominant. In the high-resistive state (HRS) C2C dispersion becomes the main source of fluctuation. A statistical procedure for the extraction of parameters of the compact model is presented. Thereby, in a circuit simulation the typical D2D and C2C fluctuations of the current-voltage (I-V) characteristics can be emulated by extracting statistical parameters of key model parameters. The statistical distributions of the parameters are used in a Monte Carlo simulation to reproduce the I-V D2D and C2C dispersions which show a good agreement to the measured curves. The results allow the simulation of the on/off current variation for the design of memory cells or can be used to emulate the synaptic behavior of these devices in artificial neural networks realized by a crossbar array of memristors.}, language = {en} }