@misc{SolanDirkmannHansenetal., author = {Solan, Enver and Dirkmann, Sven and Hansen, Mirko and Schroeder, Dietmar and Kohlstedt, Hermann and Ziegler, Martin and Mussenbrock, Thomas and Ochs, Karlheinz}, title = {An Enhanced Lumped Element Electrical Model of the Double Barrier Memristive Device}, series = {Journal of physics : D, Applied physics}, volume = {50}, journal = {Journal of physics : D, Applied physics}, number = {19}, doi = {10.1088/1361-6463/aa69ae}, pages = {10}, language = {en} } @misc{ZahariSchlichtingStrobeletal., author = {Zahari, Finn and Schlichting, Felix and Strobel, Julian and Dirkmann, Sven and Cipo, Julia and Gauter, Sven and Trieschmann, Jan and Marquardt, Richard and Haberfehlner, Georg and Kothleitner, Gerald and Kienle, Lorenz and Mussenbrock, Thomas and Ziegler, Martin and Kersten, Holger and Kohlstedt, Hermann}, title = {Correlation between sputter deposition parameters and I-V characteristics in double-barrier memristive devices}, series = {Journal of Vacuum Science \& Technology}, volume = {37}, journal = {Journal of Vacuum Science \& Technology}, number = {6}, issn = {1520-8559}, doi = {10.1116/1.5119984}, pages = {061203}, language = {en} } @misc{ZahariPerezMahadevaiahetal., author = {Zahari, Finn and P{\´e}rez, Eduardo and Mahadevaiah, Mamathamba Kalishettyhalli and Kohlstedt, Hermann and Wenger, Christian and Ziegler, Martin}, title = {Analogue pattern recognition with stochastic switching binary CMOS‑integrated memristive devices}, series = {Scientific Reports}, volume = {10}, journal = {Scientific Reports}, issn = {2045-2322}, doi = {10.1038/s41598-020-71334-x}, pages = {15}, abstract = {Biological neural networks outperform todays computer technology in terms of power consumption and computing speed when associative tasks, like pattern recognition, are to be solved. The analogue and massive parallel in-memory computing in biology differs strongly with conventional transistor electronics using the von Neumann architecture. Therefore, novel bio-inspired computing architectures are recently highly investigated in the area of neuromorphic computing. Here, memristive devices, which serve as non-volatile resistive memory, are used to emulate the plastic behaviour of biological synapses. In particular, CMOS integrated resistive random access memory (RRAM) devices are promising candidates to extend conventional CMOS technology in neuromorphic systems. However, dealing with the inherent stochasticity of the resistive switching effect can be challenging for network performance. In this work, the probabilistic switching is exploited to emulate stochastic plasticity with fully CMOS integrated binary RRAM devices. Two different RRAM technologies with different device variabilities are investigated in detail and their use in a stochastic artificial neural network (StochANN) to solve the MINST pattern recognition task is examined. A mixed-signal implementation with hardware synapses and software neurons as well as numerical simulations show the proposed concept of stochastic computing is able to handle analogue data with binary memory cells.}, language = {en} } @misc{NikiruyPerezBaronietal., author = {Nikiruy, Kristina and P{\´e}rez, Eduardo and Baroni, Andrea and Dorai Swamy Reddy, Keerthi and Pechmann, Stefan and Wenger, Christian and Ziegler, Martin}, title = {Blooming and pruning: learning from mistakes with memristive synapses}, series = {Scientific Reports}, volume = {14}, journal = {Scientific Reports}, number = {1}, issn = {2045-2322}, doi = {10.1038/s41598-024-57660-4}, abstract = {AbstractBlooming and pruning is one of the most important developmental mechanisms of the biological brain in the first years of life, enabling it to adapt its network structure to the demands of the environment. The mechanism is thought to be fundamental for the development of cognitive skills. Inspired by this, Chialvo and Bak proposed in 1999 a learning scheme that learns from mistakes by eliminating from the initial surplus of synaptic connections those that lead to an undesirable outcome. Here, this idea is implemented in a neuromorphic circuit scheme using CMOS integrated HfO2-based memristive devices. The implemented two-layer neural network learns in a self-organized manner without positive reinforcement and exploits the inherent variability of the memristive devices. This approach provides hardware, local, and energy-efficient learning. A combined experimental and simulation-based parameter study is presented to find the relevant system and device parameters leading to a compact and robust memristive neuromorphic circuit that can handle association tasks.}, language = {en} } @misc{SpetzlerFritscherParketal., author = {Spetzler, Benjamin and Fritscher, Markus and Park, Seongae and Kim, Nayoun and Wenger, Christian and Ziegler, Martin}, title = {AI-driven model for optimized pulse programming of memristive devices}, series = {APL Machine Learning}, volume = {3}, journal = {APL Machine Learning}, number = {2}, publisher = {AIP Publishing}, issn = {2770-9019}, doi = {10.1063/5.0251113}, pages = {1 -- 7}, abstract = {Next-generation artificial intelligence (AI) hardware based on memristive devices offers a promising approach to reducing the increasingly large energy consumption of AI applications. However, programming memristive AI hardware to achieve a desired synaptic weight configuration remains challenging because it requires accurate and energy-efficient algorithms for selecting the optimal weight-update pulses. Here, we present a computationally efficient AI model for predicting the weight update of memristive devices and guiding device programming. The synaptic weight-update behavior of bilayer HfO2/TiO2 memristive devices is characterized over a range of pulse parameters to provide experimental data for the AI model. Three different artificial neural network (ANN) configurations are trained and evaluated regarding the amount of training data required for accurate predictions and the computational costs. Finally, we apply the model to an antipulse weight-update process to demonstrate its performance. The results show that accurate and computationally inexpensive predictions are possible with comparatively few datasets and small ANNs. The normalized weight-update processes are predicted with accuracies comparable with larger model architectures but require only 896 floating point operations and 8.33 nJ per inference. This makes the model a promising candidate for integration into AI-driven device controllers as a precise and energy-efficient solution for memristive device programming.}, language = {en} }