@misc{RizziBaroniGlukhovetal., author = {Rizzi, Tommaso and Baroni, Andrea and Glukhov, Artem and Bertozzi, Davide and Wenger, Christian and Ielmini, Daniele and Zambelli, Cristian}, title = {Process-Voltage-Temperature Variations Assessment in Energy-Aware Resistive RAM-Based FPGAs}, series = {IEEE Transactions on Device and Materials Reliability}, volume = {23}, journal = {IEEE Transactions on Device and Materials Reliability}, number = {3}, issn = {1530-4388}, doi = {10.1109/TDMR.2023.3259015}, pages = {328 -- 336}, abstract = {Resistive Random Access Memory (RRAM) technology holds promises to improve the Field Programmable Gate Array (FPGA) performance, reduce the area footprint, and dramatically lower run-time energy requirements compared to the state-of-the-art CMOS-based products. However, the integration of RRAM in FPGAs is hindered by the high programming power consumption and by non-ideal behaviors of the device due to its stochastic nature that may overshadow the benefits in normal operation mode. To cope with these challenges, optimized programming strategies have to be investigated. In this work, we explore the impact that different procedures to set the device have on the run-time performance. Process, voltage, and temperature (PVT) variations as well as time-dependent drift effect of the RRAM device are considered in the assessment of 4T1R MUX designs characteristics. The comparison with tradition CMOS implementations reveals how the choice of the target resistive state and the programming algorithm are key design aspects to reduce the run-time delay and energy metrics, while at the same time improving the robustness against the different sources of variations.}, language = {en} } @misc{UhlmannPerezBoschQuesadaFritscheretal., author = {Uhlmann, Max and P{\´e}rez-Bosch Quesada, Emilio and Fritscher, Markus and P{\´e}rez, Eduardo and Schubert, Markus Andreas and Reichenbach, Marc and Ostrovskyy, Philip and Wenger, Christian and Kahmen, Gerhard}, title = {One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing}, series = {21st IEEE Interregional NEWCAS Conference (NEWCAS)}, journal = {21st IEEE Interregional NEWCAS Conference (NEWCAS)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0024-6}, issn = {2474-9672}, doi = {10.1109/NEWCAS57931.2023.10198073}, pages = {5}, abstract = {The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications.}, language = {en} } @misc{StrobelAlvaradoChavarinWengeretal., author = {Strobel, Carsten and Alvarado Chavarin, Carlos and Wenger, Christian and Albert, Matthias and Mikolajick, Thomas}, title = {Vertical Graphene-Based Transistors for Power Electronics, Optoelectronics and Radio-Frequency Applications}, series = {IEEE Nanotechnology Materials and Devices Conference (NMDC), Paestum, Italy, 22-25 October 2023}, journal = {IEEE Nanotechnology Materials and Devices Conference (NMDC), Paestum, Italy, 22-25 October 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-3546-0}, issn = {2473-0718}, doi = {10.1109/NMDC57951.2023.10344102}, pages = {196 -- 201}, abstract = {The combination of two-dimensional materials, such as graphene, with established thin films offers great opportunities for enabling next-generation vertical transistors for various applications. This paper gives a brief overview about different vertical transistor concepts using twodimensional materials proposed so far, e.g. the hot electron transistor and the Barristor. With the arrival of twodimensional materials, the hot electron transistor also experienced a revival with predicted cut-off frequencies in the THz range. The Barristor overcomes the weak current saturation of lateral graphene field-effect transistors and high on-off ratios up to 107 were demonstrated, which are suitable parameters for logic applications. By combining a semiconductor-graphene-semiconductor design of the simplest hot electron transistor with the Barristor operating principle a new device, called graphene adjustable-barriers transistor, can be realized. This new device concept provides the potential for RF, power electronics, and optoelectronic applications.}, language = {en} } @misc{MoralesMahmoodinezhadTschammeretal., author = {Morales, Carlos and Mahmoodinezhad, Ali and Tschammer, Rudi and Kosto, Yuliia and Alvarado Chavarin, Carlos and Schubert, Markus Andreas and Wenger, Christian and Henkel, Karsten and Flege, Jan Ingo}, title = {Combination of Multiple Operando and In-Situ Characterization Techniques in a Single Cluster System for Atomic Layer Deposition: Unraveling the Early Stages of Growth of Ultrathin Al2O3 Films on Metallic Ti Substrates}, series = {Inorganics}, volume = {11}, journal = {Inorganics}, number = {12}, issn = {2304-6740}, doi = {10.3390/inorganics11120477}, abstract = {This work presents a new ultra-high vacuum cluster tool to perform systematic studies of the early growth stages of atomic layer deposited (ALD) ultrathin films following a surface science approach. By combining operando (spectroscopic ellipsometry and quadrupole mass spectrometry) and in situ (X-ray photoelectron spectroscopy) characterization techniques, the cluster allows us to follow the evolution of substrate, film, and reaction intermediates as a function of the total number of ALD cycles, as well as perform a constant diagnosis and evaluation of the ALD process, detecting possible malfunctions that could affect the growth, reproducibility, and conclusions derived from data analysis. The homemade ALD reactor allows the use of multiple precursors and oxidants and its operation under pump and flow-type modes. To illustrate our experimental approach, we revisit the well-known thermal ALD growth of Al2O3 using trimethylaluminum and water. We deeply discuss the role of the metallic Ti thin film substrate at room temperature and 200 °C, highlighting the differences between the heterodeposition (<10 cycles) and the homodeposition (>10 cycles) growth regimes at both conditions. This surface science approach will benefit our understanding of the ALD process, paving the way toward more efficient and controllable manufacturing processes.}, language = {en} } @misc{CapistaLukoseMajnoonetal., author = {Capista, Daniele and Lukose, Rasuole and Majnoon, Farnaz and Lisker, Marco and Wenger, Christian and Lukosius, Mindaugas}, title = {Study on the metal -graphene contact resistance achieved with one -dimensional contact architecture}, series = {IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), Paestum, Italy, 22-25 October 2023}, journal = {IEEE Nanotechnology Materials and Devices Conference (NMDC 2023), Paestum, Italy, 22-25 October 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-3546-0}, doi = {10.1109/NMDC57951.2023.10343775}, pages = {118 -- 119}, abstract = {Graphene has always been considered as one of the materials with the greatest potential for the realization of improved microelectronic and photonic devices. But to actually reach its full potential in Si CMOS technology, graphene -based devices need to overcome different challenges. They do not only need to have better performances than standard devices, but they also need to be compatible with the production of standard Si based devices. To address the first challenge the main route requires the optimization of the contact resistance, that highly reduces the devices performance, while the second challenges requires the integration of graphene inside the standard production lines used for microelectronic. In this work we used an 8" wafer pilot -line to realize our devices and we studied the behavior of the contact resistance between metal and graphene obtained by one -dimensional contact architecture between the two materials. The contact resistance has been measured by means of Transmission Line Method (TLM) with several contact patterning.}, language = {en} } @misc{LukosiusLukoseLiskeretal., author = {Lukosius, Mindaugas and Lukose, Rasuolė and Lisker, Marco and Dubey, P. K. and Raju, A. I. and Capista, Daniele and Majnoon, Farnaz and Mai, A. and Wenger, Christian}, title = {Developments of Graphene devices in 200 mm CMOS pilot line}, series = {Proc. Nanotechnology Materials and Devices Conference (NMDC 2023),Paestum, Italy, 22-25 October 2023}, journal = {Proc. Nanotechnology Materials and Devices Conference (NMDC 2023),Paestum, Italy, 22-25 October 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-3546-0}, doi = {10.1109/NMDC57951.2023.10343569}, pages = {505 -- 506}, abstract = {Due to the unique electronic band structure, graphene has opened great potential to extend the functionality of a large variety of devices. Despite the significant progress in the fabrication of various graphene based microelectronic devices, the integration of graphene devices still lack the stability and compatibility with Si-technology processes. Therefore, the investigation and preparation of graphene devices in conditions resembling as close as possible the Si technology environment is of highest importance. This study aims to explore various aspects of graphene research on a 200mm pilot line, with a focus on simulations and fabrication of graphene modulator. To be more precise, it includes design and fabrication of the layouts, necessary mask sets, creation of the flows, fabrication, and measurements of the Gr modulators on 200 mm wafers.}, language = {en} } @misc{MaldonadoCantudoPerezetal., author = {Maldonado, David and Cantudo, Antonio and P{\´e}rez, Eduardo and Romero-Zaliz, Rocio and Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {TiN/Ti/HfO2/TiN Memristive Devices for Neuromorphic Computing: From Synaptic Plasticity to Stochastic Resonance}, series = {Frontiers in Neuroscience}, volume = {17}, journal = {Frontiers in Neuroscience}, issn = {1662-4548}, doi = {10.3389/fnins.2023.1271956}, abstract = {We characterize TiN/Ti/HfO2/TiN memristive devices for neuromorphic computing. We analyze different features that allow the devices to mimic biological synapses and present the models to reproduce analytically some of the data measured. In particular, we have measured the spike timing dependent plasticity behavior in our devices and later on we have modeled it. The spike timing dependent plasticity model was implemented as the learning rule of a spiking neural network that was trained to recognize the MNIST dataset. Variability is implemented and its influence on the network recognition accuracy is considered accounting for the number of neurons in the network and the number of training epochs. Finally, stochastic resonance is studied as another synaptic feature.It is shown that this effect is important and greatly depends on the noise statistical characteristics.}, language = {en} } @misc{PerezBoschQuesadaRizziGuptaetal., author = {Perez-Bosch Quesada, Emilio and Rizzi, Tommaso and Gupta, Aditya and Mahadevaiah, Mamathamba Kalishettyhalli and Schubert, Andreas and Pechmann, Stefan and Jia, Ruolan and Uhlmann, Max and Hagelauer, Amelie and Wenger, Christian and P{\´e}rez, Eduardo}, title = {Multi-Level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing}, series = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, journal = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0240-0}, doi = {10.1109/CDE58627.2023.10339525}, pages = {4}, abstract = {This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications. Index Terms—radiation-hard, hardness-by-design, memristive devices, Enclosed Layout Transistor, in-memory computing}, language = {en} } @misc{PerezMaldonadoMahadevaiahetal., author = {P{\´e}rez, Eduardo and Maldonado, David and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Cantudo, Antonio and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {A comparison of resistive switching parameters for memristive devices with HfO2 monolayers and Al2O3/HfO2 bilayers at the wafer scale}, series = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, journal = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0240-0}, doi = {10.1109/CDE58627.2023.10339417}, pages = {5}, abstract = {Memristive devices integrated in 200 mm wafers manufactured in 130 nm CMOS technology with two different dielectrics, namely, a HfO2 monolayer and an Al2O3/HfO2 bilayer, have been measured. The cycle-to-cycle (C2C) and device-todevice (D2D) variability have been analyzed at the wafer scale using different numerical methods to extract the set (Vset) and reset (Vreset) voltages. Some interesting differences between both technologies were found in terms of switching characteristics}, language = {en} } @misc{ReiserReichenbachRizzietal., author = {Reiser, Daniel and Reichenbach, Marc and Rizzi, Tommaso and Baroni, Andrea and Fritscher, Markus and Wenger, Christian and Zambelli, Cristian and Bertozzi, Davide}, title = {Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations}, series = {21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom}, journal = {21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3503-0024-6}, doi = {10.1109/NEWCAS57931.2023}, abstract = {In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate multi-level conductance operation. The support of drift models in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they overlook key device- and array-level parameters affecting drift resilience such as the programming algorithm of RRAM cells, the choice of target conductance states and the weight-toconductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability.}, language = {en} }