@misc{FritscherUhlmannOstrovskyyetal., author = {Fritscher, Markus and Uhlmann, Max and Ostrovskyy, Philip and Reiser, Daniel and Chen, Junchao and Wen, Jianan and Schulze, Carsten and Kahmen, Gerhard and Fey, Dietmar and Reichenbach, Marc and Krstic, Milos and Wenger, Christian}, title = {RISC-V CPU design using RRAM-CMOS standard cells}, series = {IEEE transactions on very large scale integration (VLSI) systems}, journal = {IEEE transactions on very large scale integration (VLSI) systems}, editor = {Wenger, Christian}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1063-8210}, doi = {10.1109/TVLSI.2025.3554476}, pages = {1 -- 9}, abstract = {The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25\% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7\% smaller area than the equivalent design using standard CMOS gates.}, language = {en} } @misc{StrobelChavarinKnautetal., author = {Strobel, Carsten and Chavarin, Carlos A. and Knaut, Martin and Wenger, Christian and Heinzig, Andr{\´e} and Mikolajick, Thomas}, title = {Demonstration of a graphene adjustable-barriers phototransistor with tunable ultra-high responsivity}, series = {Advanced Optical Materials}, journal = {Advanced Optical Materials}, publisher = {Wiley-VCH GmbH}, address = {Weinheim}, issn = {2195-1071}, doi = {10.1002/adom.202500344}, pages = {1 -- 9}, abstract = {The development of high-speed dual-band photodetectors with high responsivity is important for several applications such as optical communication, biomedical imaging or spectroscopy. In this work, a phototransistor with ultra-high responsivity is demonstrated, which potentially also allows for very high bandwidths. The device is called graphene adjustable-barriers phototransistor and is potentially capable for dual-band detection in the visible-infrared (VIS-IR) range. A material combination of intrinsic hydrogenated amorphous silicon, graphene, and n-type germanium (n-Ge) is used for the demonstrator. The device operation is based on the light induced modulation of the graphene Fermi energy level and Schottky barrier heights. For the first time, the functional mechanism of the device is successfully demonstrated in the VIS range with responsivities exceeding 107 A/W at a gate voltage of 20V. The bandwidth of the device is 1.2 kHz and is so far limited by the defective gate material hydrogenated amorphous silicon and relaxed feature sizes of the demonstrator. These results are an important step toward a new generation of high-responsivity high-speed photo detection devices.}, language = {en} } @misc{MoralesGertigKotetal., author = {Morales, Carlos and Gertig, Max and Kot, Małgorzata and Alvarado, Carlos and Schubert, Markus Andreas and Zoellner, Marvin Hartwig and Wenger, Christian and Henkel, Karsten and Flege, Jan Ingo}, title = {In situ X-ray photoelectron spectroscopy study of atomic layer deposited cerium oxide on SiO₂ : substrate influence on the reaction mechanism during the early stages of growth}, series = {Advanced materials interfaces}, volume = {12}, journal = {Advanced materials interfaces}, number = {5}, publisher = {Wiley}, address = {Weinheim}, issn = {2196-7350}, doi = {10.1002/admi.202400537}, pages = {1 -- 13}, abstract = {Thermal atomic layer deposition (ALD) of cerium oxide using commercial Ce(thd)4 precursor and O3 on SiO2 substrates is studied employing in-situ X-ray photoelectron spectroscopy (XPS). The system presents a complex growth behavior determined by the change in the reaction mechanism when the precursor interacts with the substrate or the cerium oxide surface. During the first growth stage, non-ALD side reactions promoted by the substrate affect the growth per cycle, the amount of carbon residue on the surface, and the oxidation degree of cerium oxide. On the contrary, the second growth stage is characterized by a constant growth per cycle in good agreement with the literature, low carbon residues, and almost fully oxidized cerium oxide films. This distinction between two growth regimes is not unique to the CeOx/SiO2 system but can be generalized to other metal oxide substrates. Furthermore, the film growth deviates from the ideal layer-by-layer mode, forming micrometric inhomogeneous and defective flakes that eventually coalesce for deposit thicknesses above 10 nm. The ALD-cerium oxide films present less order and a higher density of defects than films grown by physical vapor deposition techniques, likely affecting their reactivity in oxidizing and reducing conditions.}, language = {en} } @misc{MaldonadoAcalOrtizetal., author = {Maldonado, D. and Acal, C. and Ortiz, H. and Aguilera, A.M. and Ruiz-Castro, J.E. and Cantudo, A. and Baroni, A. and Dorai Swamy Reddy, K. and Pechmann, S. and Uhlmann, M. and Wenger, Christian and P{\´e}rez, E. and Rold{\´a}n, J.B.}, title = {A comprehensive statistical study of the post-programming conductance drift in HfO2-based memristive devices}, series = {Materials science in semiconductor processing}, volume = {196}, journal = {Materials science in semiconductor processing}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {1369-8001}, doi = {10.1016/j.mssp.2025.109668}, pages = {1 -- 8}, abstract = {The conductance drift in HfO2-based memristors is a critical reliability concern that impacts in their application in non-volatile memory and neuromorphic computing integrated circuits. In this work we present a comprehensive statistical analysis of the conductance drift behavior in resistive random access memories (RRAM) whose physics is based on valence change mechanisms. We experimentally characterize the conductance time evolution in six different resistance states and analyze the suitability of various probability distributions to model the observed variability. Our results reveal that the log-logistic probability distribution provides the best fit to the experimental data for the resistance multilevels and the measured post-programming times under consideration. Additionally, we employ an analysis of variance (ANOVA) to statistically analyze the post-programming time and current level effects on the observed variability. Finally, in the context of the Stanford compact model, we describe how variability has to be implemented to obtain the probability distribution of measured current values.}, language = {en} } @misc{RajuDubeyLukoseetal., author = {Raju, Ashraful Islam and Dubey, Pawan Kumar and Lukose, Rasuole and Wenger, Christian and Mai, Andreas and Lukosius, Mindaugas}, title = {Optimized silicon nitride-spaced graphene electro-optic modulator with high efficiency and bandwidth}, series = {Optical and quantum electronics}, volume = {57}, journal = {Optical and quantum electronics}, number = {7}, publisher = {Springer Science and Business Media LLC}, address = {Dordrecht}, issn = {1572-817X}, doi = {10.1007/s11082-025-08310-0}, pages = {1 -- 15}, abstract = {Optical modulators with high modulation efficiency, large operational bandwidth, high-speed and low energy consumption is essential for the advancement of on-chip optical signal processing. To overcome the bandwidth-efficiency trade-off in graphene optical modulators, a buried silicon nitride waveguide-coupled double-layer graphene electro-absorption (EA) optical modulator has been proposed. In the proposed design, silicon nitride layer is also embedded between the two graphene layers as a dielectric spacer to enhance the graphene-light interaction. An extensive simulation has been performed to optimize the dielectric spacing layers between the two graphene for optimal device performance including the waveguide dimensions and optical modes profile. The simulated results show a high modulation efficiency of 1.1 dB/V and a modulation depth of 0.16 dB/µm, corresponding to a 15-dB extinction ratio for a 100 µm device at 1550 nm, with a 30 nm spacer and 12 V driving voltage. The proposed modulator achieves a 14 GHz bandwidth and operates over a 1050 nm broadband operation spectral range. The concurrent presence of high modulation bandwidth and efficiency renders these modulator designs highly viable for on-chip optical communication applications.}, language = {en} } @misc{MoralesTschammerPożarowskaetal., author = {Morales, Carlos and Tschammer, Rudi and Pożarowska, Emilia and Kosto, Julia and Villar-Garcia, Ignacio J. and P{\´e}rez-Dieste, Virginia and Favaro, Marco and Starr, David E. and Kapuścik, Paulina and Mazur, Michał and Wojcieszak, Damian and Domaradzki, Jarosław and Alvarado, Carlos and Wenger, Christian and Henkel, Karsten and Flege, Jan Ingo}, title = {Hydrogen sensing via heterolytic H₂ activation at room temperature by atomic layer deposited ceria}, series = {ChemSusChem : chemistry, sustainability, energy, materials}, volume = {18}, journal = {ChemSusChem : chemistry, sustainability, energy, materials}, number = {13}, publisher = {Wiley-VCH}, address = {Weinheim}, issn = {1864-5631}, doi = {10.1002/cssc.202402342}, pages = {1 -- 13}, abstract = {Ultrathin atomic layer deposited ceria films (\<20 nm) are capable of H2 heterolytic activation at room temperature, undergoing a significant reduction regardless of the absolute pressure, as measured under in-situ conditions by near ambient pressure X-ray photoelectron spectroscopy. ALD-ceria can gradually reduce as a function of H2 concentration under H2/O2 environments, especially for diluted mixtures below 10 \%. At room temperature, this reduction is limited to the surface region, where the hydroxylation of the ceria surface induces a charge transfer towards the ceria matrix, reducing Ce4+ cations to Ce3+. Thus, ALD-ceria replicates the expected sensing mechanism of metal oxides at low temperatures without using any noble metal decorating the oxide surface to enhance H2 dissociation. The intrinsic defects of the ALD deposit seem to play a crucial role since the post-annealing process capable of healing these defects leads to decreased film reactivity. The sensing behavior was successfully demonstrated in sensor test structures by resistance changes towards low concentrations of H2 at low operating temperatures without using noble metals. These promising results call for combining ALD-ceria with more conductive metal oxides, taking advantage of the charge transfer at the interface and thus modifying the depletion layer formed at the heterojunction.}, language = {en} } @misc{FuenningPaulManganellietal., author = {F{\"u}nning, Tabea and Paul, Martin and Manganelli, Costanza Lucia and Wenger, Christian and Mai, Andreas and Steglich, Patrick}, title = {Comparative simulation analysis of photonic ultrasound sensors based on silicon waveguides}, series = {Scientific reports}, volume = {15}, journal = {Scientific reports}, number = {1}, publisher = {Springer Science and Business Media LLC}, address = {[London]}, issn = {2045-2322}, doi = {10.1038/s41598-025-01953-9}, pages = {1 -- 13}, abstract = {Pressure sensors based on photonic integrated circuits (PIC) offer the prospect of outstanding sensitivities, extreme miniaturization and have the potential for highly scalable production using CMOS compatible processing. PIC-based pressure sensors detect the change in optical properties, i.e. the intensity or phase of the optical carrier wave inside miniaturized waveguide structures. The detection of ultrasound is achieved by engineering the waveguide architecture such that a pressure causes a high change in the effective refractive index of the waveguide. A range of PIC-based pressure sensors have been reported, but a comparison of the sensitivity of the different approaches is not straightforward, since different pressure sensitive waveguide architectures as well as photonic layouts and measurement setups impact the performance. Additionally, the used sensitivity unit is not uniform throughout the different studies, further complicating a comparison. In this work, a detailed simulation study is carried out by finite element modeling of different pressure sensitive waveguide architectures for a consistent comparison. We analyze three different sensor architectures: (A) a free standing membrane located within a tiny air gap above the waveguide, (B) a waveguide located on top of a deflectable membrane as well as (C) a waveguide embedded inside a pressure-sensitive polymer cladding. The mechanical response of the structures and the resulting changes in mode propagation, i.e. the change of the effective refractive index, are analyzed. The waveguide sensitivities in RIU/MPa for different waveguide types (strip, slot) and polarization states (TE, TM) are compared. The results reveal inherent limitations of the different waveguide designs and create a basis for the selection of suitable designs for further ultrasound sensor development. Possibilities for enhancing waveguide sensitivity are identified and discussed. Additionally, we have shown that the studied approaches are extensible to SiN waveguides.}, language = {en} } @misc{UhlmannKrysikWenetal., author = {Uhlmann, Max and Krysik, Milosz and Wen, Jianan and Frohberg, Max and Baroni, Andrea and Reddy, Keerthi Dorai Swamy and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Piotrowski, Krzysztof and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard}, title = {A compact one-transistor-multiple-RRAM characterization platform}, series = {IEEE transactions on circuits and systems I : regular papers}, journal = {IEEE transactions on circuits and systems I : regular papers}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1549-8328}, doi = {10.1109/TCSI.2025.3555234}, pages = {1 -- 12}, abstract = {Emerging non-volatile memories (eNVMs) such as resistive random-access memory (RRAM) offer an alternative solution compared to standard CMOS technologies for implementation of in-memory computing (IMC) units used in artificial neural network (ANN) applications. Existing measurement equipment for device characterisation and programming of such eNVMs are usually bulky and expensive. In this work, we present a compact size characterization platform for RRAM devices, including a custom programming unit IC that occupies less than 1 mm2 of silicon area. Our platform is capable of testing one-transistor-one-RRAM (1T1R) as well as one-transistor-multiple-RRAM (1TNR) cells. Thus, to the best knowledge of the authors, this is the first demonstration of an integrated programming interface for 1TNR cells. The 1T2R IMC cells were fabricated in the IHP's 130 nm BiCMOS technology and, in combination with other parts of the platform, are able to provide more synaptic weight resolution for ANN model applications while simultaneously decreasing the energy consumption by 50 \%. The platform can generate programming voltage pulses with a 3.3 mV accuracy. Using the incremental step pulse with verify algorithm (ISPVA) we achieve 5 non-overlapping resistive states per 1T1R device. Based on those 1T1R base states we measure 15 resulting state combinations in the 1T2R cells.}, language = {en} } @misc{BaroniPerezReddyetal., author = {Baroni, Andrea and P{\´e}rez, Eduardo and Reddy, Keerthi Dorai Swamy and Pechmann, Stefan and Wenger, Christian and Ielmini, Daniele and Zambelli, Cristian}, title = {Enhancing RRAM reliability : exploring the effects of Al doping on HfO2-based devices}, series = {IEEE transactions on device and materials reliability}, journal = {IEEE transactions on device and materials reliability}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1530-4388}, doi = {10.1109/TDMR.2025.3581061}, pages = {1 -- 9}, abstract = {This study provides a comprehensive evaluation of RRAM devices based on HfO2 and Al-doped HfO2 insulators, focusing on critical performance metrics, including Forming yield, Post-Programming Stability (PPS), Fast Drift, Endurance, and Retention at elevated temperatures (125 ∘C). Aluminum doping significantly enhances device reliability and stability, improving Forming yield, reducing current drift during programming and Retention tests, and minimizing variability during Endurance cycling. While Al5\%:HfO2 achieves most of the observed benefits compared to pure HfO2, Al7\%:HfO2 offers incremental advantages for scenarios requiring extreme reliability. These findings position Al-doped HfO2 devices as a promising solution for RRAM-based systems in memory and neuromorphic computing, highlighting the potential trade-off between performance gains and increased fabrication complexity. This work underlines the importance of material engineering for optimizing RRAM devices in application-specific contexts.}, language = {en} } @misc{UhlmannRizziWenetal., author = {Uhlmann, Max and Rizzi, Tommaso and Wen, Jianan and Quesada, Emilio P{\´e}rez-Bosch and Beattie, Bakr Al and Ochs, Karlheinz and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard}, title = {End-to-end design flow for resistive neural accelerators}, series = {IEEE transactions on computer-aided design of integrated circuits and systems}, journal = {IEEE transactions on computer-aided design of integrated circuits and systems}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {0278-0070}, doi = {10.1109/TCAD.2025.3597237}, pages = {1 -- 5}, abstract = {Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed towards leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP's one-transistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators.}, language = {en} } @misc{BlumensteinPerezWengeretal., author = {Blumenstein, Alan and P{\´e}rez, Eduardo and Wenger, Christian and Dersch, Nadine and Kloes, Alexander and I{\~n}{\´i}guez, Benjam{\´i}n and Schwarz, Mike}, title = {Evaluating device variability in RRAM-based single- and multi-layer perceptrons}, series = {2025 32nd International Conference on Mixed Design of Integrated Circuits and System (MIXDES)}, journal = {2025 32nd International Conference on Mixed Design of Integrated Circuits and System (MIXDES)}, publisher = {IEEE}, address = {New York}, isbn = {978-83-63578-27-5}, doi = {10.23919/MIXDES66264.2025.11092102}, pages = {74 -- 77}, abstract = {This work investigates the impact of stochastic weight variations in hardware implementations of artificial neural networks, focusing on a Single-Layer Perceptron and Multi-Layer Perceptrons. A variable neural network model is introduced, applying Gaussian variability to synaptic weights based on an adjustment rate, which controls the proportion of affected weights. By studying how stochastic variations affect accuracy, simulations under device-to-device and cycle-to-cycle variation conditions demonstrate that Single-Layer Perceptrons are more sensitive to weight variations, while Multi-Layer perceptrons show greater robustness. Additionally, stochastic quantization improves the performance of Multi-Layer Perceptrons but has minimal effect on Single-Layer Perceptrons.}, language = {en} }