@misc{VenkateshaPitonakKillat, author = {Venkatesha, Shishira S. and Pitonak, Pavol and Killat, Dirk}, title = {Active and continuous compensation of clock jitter in CT Delta-Sigma ADCs}, series = {3rd URSI Atlantic and Asia Pacific Radio Science Meeting, 30 May - 04 June 2022, Gran Canaria, Spain}, journal = {3rd URSI Atlantic and Asia Pacific Radio Science Meeting, 30 May - 04 June 2022, Gran Canaria, Spain}, publisher = {IEEE Explore}, isbn = {978-9-4639-6-8058}, doi = {10.23919/AT-AP-RASC54737.2022.9814404}, pages = {4}, language = {en} } @misc{VenkateshaKillat, author = {Venkatesha, Shishira S. and Killat, Dirk}, title = {A fully differential 3-stage CMOS op-amp for high-speed sampling applications}, series = {2023 Kleinheubach Conference, September 26 - 28, 2023, Miltenberg, Germany}, journal = {2023 Kleinheubach Conference, September 26 - 28, 2023, Miltenberg, Germany}, publisher = {IEEE}, address = {Piscataway}, isbn = {978-3-948571-08-5}, pages = {1 -- 4}, language = {en} } @misc{VenkateshaKillat, author = {Venkatesha, Shishira S and Killat, Dirk}, title = {Design of a fully differential track-and-hold amplifier}, series = {2025 Kleinheubach Conference}, journal = {2025 Kleinheubach Conference}, publisher = {IEEE}, address = {Piscataway, NJ}, doi = {10.23919/IEEECONF67516.2025.11225213}, pages = {1 -- 4}, abstract = {This paper presents a fully differential track-and-hold amplifier (THA) architecture for high-speed applications. The proposed design employs a distinctive switching arrangement that converts non-linear errors into a constant offset and provides an initialization sub-phase before tracking. The circuit utilizes two capacitors in the signal path to enable gain flexibility, providing an accurate output during hold mode. The THA was implemented in 65-nm CMOS technology with a 1.2 V supply voltage. The results of the simulation after layout demonstrate a droop rate of 2.5mV/μS, a hold-mode settling time of 2ns for a 1pF hold capacitor.}, language = {en} }