@misc{PechmannMaiVoelkeletal., author = {Pechmann, Stefan and Mai, Timo and V{\"o}lkel, Matthias and Mahadevaiah, Mamathamba Kalishettyhalli and P{\´e}rez, Eduardo and Perez-Bosch Quesada, Emilio and Reichenbach, Marc and Wenger, Christian and Hagelauer, Amelie}, title = {A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells}, series = {Electronics}, volume = {10}, journal = {Electronics}, number = {5}, issn = {2079-9292}, doi = {10.3390/electronics10050530}, pages = {17}, abstract = {In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.}, language = {en} } @misc{PechmannMaiPotschkaetal., author = {Pechmann, Stefan and Mai, Timo and Potschka, Julian and Reiser, Daniel and Reichel, Peter and Breiling, Marco and Reichenbach, Marc and Hagelauer, Amelie}, title = {A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks}, series = {Micromachines}, volume = {12}, journal = {Micromachines}, number = {11}, issn = {2072-666X}, doi = {10.3390/mi12111277}, url = {http://nbn-resolving.de/urn:nbn:de:bvb:29-opus4-174878}, language = {en} } @misc{SuawaFogouMeiselJongmannsetal., author = {Suawa Fogou, Priscile and Meisel, Tenia and Jongmanns, Marcel and H{\"u}bner, Michael and Reichenbach, Marc}, title = {Modeling and Fault Detection of Brushless Direct Current Motor by Deep Learning Sensor Data Fusion}, series = {Sensors}, volume = {22}, journal = {Sensors}, number = {9}, issn = {1424-8220}, doi = {10.3390/s22093516}, pages = {17}, language = {en} } @misc{FritscherKnoedtelMallahetal., author = {Fritscher, Markus and Kn{\"o}dtel, Johannes and Mallah, Maen and Pechmann, Stefan and Perez-Bosch Quesada, Emilio and Rizzi, Tommaso and Wenger, Christian and Reichenbach, Marc}, title = {Mitigating the Effects of RRAM Process Variation on the Accuracy of Artifical Neural Networks}, series = {Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science}, journal = {Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2021. Lecture Notes in Computer Science}, publisher = {Springer}, isbn = {978-3-031-04579-0}, issn = {0302-9743}, doi = {10.1007/978-3-031-04580-6_27}, pages = {401 -- 417}, abstract = {Weight storage is a key challenge in the efficient implementation of artificial neural networks. Novel memory technologies such as RRAM are able to greatly improve density and introduce non-volatility and multibit capabilities to this component of ANN accelerators. The usage of RRAM in this domain comes with downsides, mainly caused by cycle-to-cycle and device-to-device variability leading to erroneous readouts, greatly affecting digital systems. ANNs have the ability to compensate for this by their inherent redundancy and usually exhibit a gradual deterioration in the accuracy of the task at hand. This means, that slight error rates can be acceptable for weight storage in an ANN accelerator. In this work we link device-to-device variability to the accuracy of an ANN for such an accelerator. From this study, we can estimate how strongly a certain net is affected by a certain device parameter variability. This methodology is then used to present three mitigation strategies and to evaluate how they affect the reaction of the network to variability: a) Dropout Layers b) Fault-Aware Training c) Redundancy. These mitigations are then evaluated by their ability to improve accuracy and to lower hardware overhead by providing data for a real-word example. We improved this network's resilience in such a way that it could tolerate double the variation in one of the device parameters (standard deviation of the oxide thickness can be 0.4 nm instead of 0.2 nm while maintaining sufficient accuracy.)}, language = {en} } @misc{HernandezFrickeAlKadietal., author = {Hernandez, Hector Gerardo Mu{\~n}oz and Fricke, Florian and Al Kadi, Muhammed and Reichenbach, Marc and H{\"u}bner, Michael}, title = {Edge GPU based on an FPGA Overlay Architecture using PYNQ}, series = {35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI). 2022}, journal = {35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI). 2022}, isbn = {978-1-6654-8128-1}, doi = {10.1109/SBCCI55532.2022.9893229}, pages = {6}, language = {en} } @misc{SuawaFogouHalbingerJongmannsetal., author = {Suawa Fogou, Priscile and Halbinger, Anja and Jongmanns, Marcel and Reichenbach, Marc}, title = {Noise-Robust Machine Learning Models for Predictive Maintenance Applications}, series = {IEEE Sensors Journal}, volume = {23}, journal = {IEEE Sensors Journal}, number = {13}, issn = {1558-1748}, doi = {10.1109/JSEN.2023.3273458}, pages = {15081 -- 15092}, abstract = {Predictive maintenance of equipment requires a set of data collected through sensors, from which models will learn behaviors that will allow the automatic detection or prediction of these behaviors. The objective is to anticipate unexpected situations such as sudden equipment stoppages. Industries are noisy environments due to production lines that involve a series of components. As a result, the data will always be obstructed by noise. Noise-robust predictive maintenance models, which include ensemble and deep learning models with and without data fusion, are proposed to enhance the monitoring of industrial equipment. The work reported in this article is based on two components, a milling tool, and a motor, with sound, vibration, and ultrasound data collected in real experiments. Four main tasks were performed, namely the construction of the datasets, the training of the monitoring models without adding artificial noise to the data, the evaluation of the robustness of the previously trained models by injecting several levels of noise into the test data, and the optimization of the models by a proposed noisy training approach. The results show that the models maintain their performances at over 95\% accuracy despite adding noise in the test phase. These performances decrease by only 2\% at a considerable noise level of 15-dB signal-to-noise ratio (SNR). The noisy training method proved to be an optimal solution for improving the noise robustness and accuracy of convolutional deep learning models, whose performance regression of 2\% went from a noise level of 28 to 15 dB like the other models.}, language = {en} } @misc{AssafoLautschSuawaetal., author = {Assafo, Maryam and Lautsch, Martin and Suawa, Priscile Fogou and Jongmanns, Marcel and H{\"u}bner, Michael and Reichenbach, Marc and Brockmann, Carsten and Reinhardt, Denis and Langend{\"o}rfer, Peter}, title = {The ForTune Toolbox: Building Solutions for Condition-Based and Predictive Maintenance Focusing on Retrofitting}, publisher = {VDE Verlag}, address = {Berlin}, isbn = {978-3-8007-6204-0}, pages = {S. 541}, language = {en} } @misc{FrickeScharobaRachujetal., author = {Fricke, Florian and Scharoba, Stefan and Rachuj, Sebastian and Konopik, Andreas and Kluge, Florian and Hofstetter, Georg and Reichenbach, Marc}, title = {Application Runtime Estimation for AURIX Embedded MCU Using Deep Learning }, series = {Embedded computer systems : architectures, modeling, and simulation : 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, proceedings}, journal = {Embedded computer systems : architectures, modeling, and simulation : 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, proceedings}, editor = {Orailoglu, Alex and Reichenbach, Marc and Jung, Matthias}, publisher = {Springer}, address = {Cham}, isbn = {978-3-031-15073-9}, doi = {10.1007/978-3-031-15074-6_15}, pages = {235 -- 249}, language = {en} } @misc{MahmoodScharobaSchorlemeretal., author = {Mahmood, Safdar and Scharoba, Stefan and Schorlemer, Jonas and Schulz, Christian and H{\"u}bner, Michael and Reichenbach, Marc}, title = {Detecting Improvised Land-mines using Deep Neural Networks on GPR Image Dataset targeting FPGAs }, series = {IEEE Nordic Circuits and Systems Conference (NORCAS), 25-26 October 2022, Oslo, Norway}, journal = {IEEE Nordic Circuits and Systems Conference (NORCAS), 25-26 October 2022, Oslo, Norway}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3503-4550-6}, doi = {10.1109/norcas57515.2022.9934735}, pages = {1 -- 7}, language = {en} } @misc{MahmoodHuebnerReichenbach, author = {Mahmood, Safdar and H{\"u}bner, Michael and Reichenbach, Marc}, title = {A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing}, series = {Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023}, journal = {Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023}, editor = {Palumbo, Francesca and Keramidas, Georgios and Voros, Nikolaos and Diniz, Pedro C.}, publisher = {Springer}, address = {Cham}, isbn = {978-3-031-42921-7}, doi = {10.1007/978-3-031-42921-7_27}, pages = {371 -- 374}, language = {en} } @inproceedings{WenVargasZhuetal., author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and P{\´e}rez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos}, title = {Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment}, series = {2024 IEEE 25th Latin American Test Symposium (LATS)}, booktitle = {2024 IEEE 25th Latin American Test Symposium (LATS)}, publisher = {IEEE}, doi = {10.1109/LATS62223.2024.10534601}, pages = {6}, abstract = {Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation.}, language = {en} } @misc{FritscherSinghRizzietal., author = {Fritscher, Markus and Singh, Simranjeet and Rizzi, Tommaso and Baroni, Andrea and Reiser, Daniel and Mallah, Maen and Hartmann, David and Bende, Ankit and Kempen, Tim and Uhlmann, Max and Kahmen, Gerhard and Fey, Dietmar and Rana, Vikas and Menzel, Stephan and Reichenbach, Marc and Krstic, Milos and Merchant, Farhad and Wenger, Christian}, title = {A flexible and fast digital twin for RRAM systems applied for training resilient neural networks}, series = {Scientific Reports}, volume = {14}, journal = {Scientific Reports}, number = {1}, publisher = {Springer Science and Business Media LLC}, issn = {2045-2322}, doi = {10.1038/s41598-024-73439-z}, pages = {13}, abstract = {Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the "ideal memristor" which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a "push button" modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).}, language = {en} } @misc{FritscherUhlmannOstrovskyyetal., author = {Fritscher, Markus and Uhlmann, Max and Ostrovskyy, Philip and Reiser, Daniel and Chen, Junchao and Schubert, Andreas and Schulze, Carsten and Kahmen, Gerhard and Fey, Dietmar and Reichenbach, Marc and Krstic, Milos and Wenger, Christian}, title = {Area-efficient digital design using RRAM-CMOS standard cells}, series = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, volume = {18}, journal = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, publisher = {IEEE}, isbn = {979-8-3503-5411-9}, issn = {2159-3477}, doi = {10.1109/ISVLSI61997.2024.00026}, pages = {81 -- 87}, abstract = {Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 \% smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 \%. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core.}, language = {en} } @misc{VishwakarmaFritscherHagelaueretal., author = {Vishwakarma, Abhinav and Fritscher, Markus and Hagelauer, Amelie and Reichenbach, Marc}, title = {An RRAM-based building block for reprogrammable non-uniform sampling ADCs}, series = {Information Technology : it}, volume = {65}, journal = {Information Technology : it}, number = {1-2}, issn = {2196-7032}, doi = {10.1515/itit-2023-0021}, pages = {39 -- 51}, language = {en} } @misc{SchlipfBerkmannYamamotoetal., author = {Schlipf, Jon and Berkmann, Fritz and Yamamoto, Yuji and Reichenbach, Marc and Veleski, Mitko and Kawaguchi, Yuma and M{\"o}rz, Florian and Tomm, Jens W. and Weißhaupt, David and Fischer, Inga Anita}, title = {Robust Si/Ge heterostructure metasurfaces as building blocks for wavelength-selective photodetectors}, series = {Applied Physics Letters}, volume = {122}, journal = {Applied Physics Letters}, number = {12}, issn = {1077-3118}, doi = {10.1063/5.0134458}, language = {en} } @misc{KnoedtelRachujReichenbach, author = {Kn{\"o}dtel, Johannes and Rachuj, Sebastian and Reichenbach, Marc}, title = {Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best?}, series = {25th Euromicro Conference on Digital System Design (DSD), 31 August 2022 - 02 September 2022, Maspalomas, Spain}, journal = {25th Euromicro Conference on Digital System Design (DSD), 31 August 2022 - 02 September 2022, Maspalomas, Spain}, publisher = {IEEE}, doi = {10.1109/DSD57027.2022.00041}, pages = {247 -- 253}, language = {en} } @misc{ShahinRottaArchilaetal., author = {Shahin, Keyvan and Rotta, Randolf and Archila, Oscar and Mykytyn, Pavlo and Nattke, Matthias and Reichenbach, Marc and Nolte, J{\"o}rg and Natarov, Roman}, title = {A Modular Communication Architecture for Adaptive UAV Swarms}, series = {2023 IEEE International Conference on Omni-layer Intelligent Systems (COINS)}, journal = {2023 IEEE International Conference on Omni-layer Intelligent Systems (COINS)}, publisher = {IEEE}, address = {Berlin}, isbn = {979-8-3503-4647-3}, doi = {10.1109/COINS57856.2023.10189245}, pages = {6}, abstract = {Small Unmanned Aerial Vehicles (UAVs) have vast application potential from industrial logistics and disaster monitoring to smart farming, for example, to create maps with Normalized Difference Vegetation Index (NDVI) cameras and AI-based image classification or the precision spot application of fertilizers. Operating multiple UAVs in parallel, including those with different specializations, enables efficient coverage of large areas. While existing research focused mainly on predefined flight formations for swarms or autonomous missions for single UAVs, the focus of this work is on multiple UAVs with individually adaptable missions. We derive communication system requirements from swarm coordination algorithms and present a respective design. The resulting modular architecture enables future research on autonomous adaptive UAV swarms and their use as flying sensor platforms.}, language = {en} } @misc{UhlmannPerezBoschQuesadaFritscheretal., author = {Uhlmann, Max and P{\´e}rez-Bosch Quesada, Emilio and Fritscher, Markus and P{\´e}rez, Eduardo and Schubert, Markus Andreas and Reichenbach, Marc and Ostrovskyy, Philip and Wenger, Christian and Kahmen, Gerhard}, title = {One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing}, series = {21st IEEE Interregional NEWCAS Conference (NEWCAS)}, journal = {21st IEEE Interregional NEWCAS Conference (NEWCAS)}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0024-6}, issn = {2474-9672}, doi = {10.1109/NEWCAS57931.2023.10198073}, pages = {5}, abstract = {The use of resistive random-access memory (RRAM) for in-memory computing (IMC) architectures has significantly improved the energy-efficiency of artificial neural networks (ANN) over the past years. Current RRAM-technologies are physically limited to a defined unambiguously distinguishable number of stable states and a maximum resistive value and are compatible with present complementary metal-oxide semiconductor (CMOS)-technologies. In this work, we improved the accuracy of current ANN models by using increased weight resolutions of memristive devices, combining two or more in-series RRAM cells, integrated in the back end of line (BEOL) of the CMOS process. Based on system level simulations, 1T2R devices were fabricated in IHP's 130nm SiGe:BiCMOS technology node, demonstrating an increased number of states. We achieved an increase in weight resolution from 3 bit in ITIR cells to 6.5 bit in our 1T2R cell. The experimental data of 1T2R devices gives indications for the performance and energy-efficiency improvement in ITNR arrays for ANN applications.}, language = {en} } @misc{SchwengerHolzingerFeyetal., author = {Schwenger, Lars and Holzinger, Philipp and Fey, Dietmar and Munoz-Hernandez, Hector Gerardo and Reichenbach, Marc}, title = {EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-Synthesis}, series = {Embedded computer systems : architectures, modeling, and simulation : 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, proceedings}, journal = {Embedded computer systems : architectures, modeling, and simulation : 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, proceedings}, editor = {Orailoglu, Alex and Reichenbach, Marc and Jung, Matthias}, publisher = {Springer}, address = {Cham}, isbn = {978-3-031-15073-9}, pages = {43 -- 60}, language = {en} } @misc{KnoedtelMunozHernandezLehnertetal., author = {Kn{\"o}dtel, Johannes and Munoz-Hernandez, Hector Gerardo and Lehnert, Alexander and Thieu, Gia Bao and Gesper, Sven and Pay{\´a}-Vay{\´a}, Guillermo and Reichenbach, Marc}, title = {TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs}, series = {Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings}, journal = {Applied Reconfigurable Computing. Architectures, Tools, and Applications, 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings}, editor = {Palumbo, Francesca and Keramidas, Georgios and Voros, Nikolaos and Diniz, Pedro C.}, publisher = {Springer}, address = {Cham}, isbn = {978-3-031-42920-0}, doi = {10.1007/978-3-031-42921-7_21}, pages = {307 -- 321}, language = {en} } @misc{ReiserReichenbachRizzietal., author = {Reiser, Daniel and Reichenbach, Marc and Rizzi, Tommaso and Baroni, Andrea and Fritscher, Markus and Wenger, Christian and Zambelli, Cristian and Bertozzi, Davide}, title = {Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations}, series = {21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom}, journal = {21st IEEE Interregional NEWCAS Conference (NEWCAS), 26-28 June 2023, Edinburgh, United Kingdom}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3503-0024-6}, doi = {10.1109/NEWCAS57931.2023}, abstract = {In-memory computing with resistive-switching random access memory (RRAM) crossbar arrays has the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. However, RRAM devices are subject to several non-idealities that result in significant inference accuracy drops compared with software baseline accuracy. A critical one is related to the drift of the conductance states appearing immediately at the end of program and verify algorithms that are mandatory for accurate multi-level conductance operation. The support of drift models in state-of-the-art simulation tools of memristive computationin-memory is currently only in the early stage, since they overlook key device- and array-level parameters affecting drift resilience such as the programming algorithm of RRAM cells, the choice of target conductance states and the weight-toconductance mapping scheme. The goal of this paper is to fully expose these parameters to RRAM crossbar designers as a multi-dimensional optimization space of drift resilience. For this purpose, a simulation framework is developed, which comes with the suitable abstractions to propagate the effects of those RRAM crossbar configuration parameters to their ultimate implications over inference performance stability.}, language = {en} }