@misc{SegabinazziFerreiraNolte, author = {Segabinazzi Ferreira, Raphael and Nolte, J{\"o}rg}, title = {Low latency reconfiguration mechanism for fine-grained processor internal functional units}, series = {2019 IEEE Latin American Test Symposium (LATS)}, journal = {2019 IEEE Latin American Test Symposium (LATS)}, isbn = {978-1-7281-1756-0}, issn = {2373-0862}, doi = {10.1109/LATW.2019.8704560}, pages = {6}, abstract = {The strive for performance, low power consumption, and less chip area have been diminishing the reliability and the time to fault occurrences due to wear out of electronic devices. Recent research has shown that functional units within processors usually execute a different amount of operations when running programs. Therefore, these units present different individual wear out during their lifetime. Most existent schemes for reconfiguration of processors due to fault detection and other processor parameters are done at the level of cores which is a costly way to achieve redundancy. This paper presents a low latency (approximately 1 clock cycle) software controlled mechanism to reconfigure units within processor cores according to predefined parameters. Such reconfiguration capability delivers features like wear out balance of processor functional units, configuration of units according to the criticality of tasks running on an operating system and configurations to gain in performance (e.g. parallel execution) when possible. The focus of this paper is to show the implemented low latency reconfiguration mechanism and highlight its possible main features.}, language = {en} } @misc{SegabinazziFerreiraGeorgeChenetal., author = {Segabinazzi Ferreira, Raphael and George, Nevin and Chen, Junchao and H{\"u}bner, Michael and Krstic, Milos and Nolte, J{\"o}rg and Vierhaus, Heinrich Theodor}, title = {Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness}, series = {Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design}, journal = {Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design}, publisher = {SEA-Publications}, address = {Kallithea, Chalkidiki (Greece)}, isbn = {978-3-902457-54-7}, doi = {10.26127/BTUOpen-5050}, pages = {2}, abstract = {Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on- line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system.}, language = {en} } @misc{SegabinazziFerreiraNolteVargasetal., author = {Segabinazzi Ferreira, Raphael and Nolte, J{\"o}rg and Vargas, Fabian and George, Nevin and H{\"u}bner, Michael}, title = {Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications}, series = {IEEE Latin American Test Symposium (LATS), Macei{\´o}, Brazil}, journal = {IEEE Latin American Test Symposium (LATS), Macei{\´o}, Brazil}, doi = {10.1109/LATS49555.2020.9093692}, pages = {6}, language = {en} } @misc{RottaSegabinazziFerreiraNolte, author = {Rotta, Randolf and Segabinazzi Ferreira, Raphael and Nolte, J{\"o}rg}, title = {Real-time dynamic hardware reconfiguration for processors with redundant functional units}, series = {Proceedings of the 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC)}, journal = {Proceedings of the 2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC)}, publisher = {Institute of Electrical and Electronics Engineers Inc. (IEEE)}, address = {Nashville, TN, USA}, isbn = {978-1-7281-6958-3}, issn = {2375-5261}, doi = {10.1109/ISORC49007.2020.00035}, pages = {2}, abstract = {The tiny logic elements in modern integrated circuits increase the rate of transient failures significantly. Therefore, redundancy on various levels is necessary to retain reliability. However, for mixed-criticality scenarios, the typical processor designs offer either too little fault-tolerance or too much redundancy for one part of the applications. Amongst others, we specifically address redundant processor internal functional units (FU) to cope with transient errors and support wear leveling. A real-time operating system (RTOS) was extended to control our prototypical hardware platform and, since it can be configured deterministically within few clock cycles, we are able to reconfigure the FUs dynamically, at process switching time, according to the specified critically of the running processes. Our mechanisms were integrated into the Plasma processor and the Plasma-RTOS. With few changes to the original software code, it was, for example, possible to quickly change from fault-detecting to fault-correcting modes of the processor on demand.}, language = {en} }