@misc{PerezMaldonadoMahadevaiahetal., author = {P{\´e}rez, Eduardo and Maldonado, David and Mahadevaiah, Mamathamba Kalishettyhalli and Perez-Bosch Quesada, Emilio and Cantudo, Antonio and Jimenez-Molinos, Francisco and Wenger, Christian and Roldan, Juan Bautista}, title = {A comparison of resistive switching parameters for memristive devices with HfO2 monolayers and Al2O3/HfO2 bilayers at the wafer scale}, series = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, journal = {14th Spanish Conference on Electron Devices (CDE 2023), Valencia, Spain, 06-08 June 2023}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, isbn = {979-8-3503-0240-0}, doi = {10.1109/CDE58627.2023.10339417}, pages = {5}, abstract = {Memristive devices integrated in 200 mm wafers manufactured in 130 nm CMOS technology with two different dielectrics, namely, a HfO2 monolayer and an Al2O3/HfO2 bilayer, have been measured. The cycle-to-cycle (C2C) and device-todevice (D2D) variability have been analyzed at the wafer scale using different numerical methods to extract the set (Vset) and reset (Vreset) voltages. Some interesting differences between both technologies were found in terms of switching characteristics}, language = {en} } @misc{UhlmannRizziWenetal., author = {Uhlmann, Max and Rizzi, Tommaso and Wen, Jianan and Quesada, Emilio P{\´e}rez-Bosch and Beattie, Bakr Al and Ochs, Karlheinz and P{\´e}rez, Eduardo and Ostrovskyy, Philip and Carta, Corrado and Wenger, Christian and Kahmen, Gerhard}, title = {End-to-end design flow for resistive neural accelerators}, series = {IEEE transactions on computer-aided design of integrated circuits and systems}, journal = {IEEE transactions on computer-aided design of integrated circuits and systems}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {0278-0070}, doi = {10.1109/TCAD.2025.3597237}, pages = {1 -- 5}, abstract = {Neural hardware accelerators have demonstrated notable energy efficiency in tackling tasks, which can be adapted to artificial neural network (ANN) structures. Research is currently directed towards leveraging resistive random-access memories (RRAMs) among various memristive devices. In conjunction with complementary metal-oxide semiconductor (CMOS) technologies within integrated circuits (ICs), RRAM devices are used to build such neural accelerators. In this study, we present a neural accelerator hardware design and verification flow, which uses a lookup table (LUT)-based Verilog-A model of IHP's one-transistor-one-RRAM (1T1R) cell. In particular, we address the challenges of interfacing between abstract ANN simulations and circuit analysis by including a tailored Python wrapper into the design process for resistive neural hardware accelerators. To demonstrate our concept, the efficacy of the proposed design flow, we evaluate an ANN for the MNIST handwritten digit recognition task, as well as for the CIFAR-10 image recognition task, with the last layer verified through circuit simulation. Additionally, we implement different versions of a 1T1R model, based on quasi-static measurement data, providing insights on the effect of conductance level spacing and device-to-device variability. The circuit simulations tackle both schematic and physical layout assessment. The resulting recognition accuracies exhibit significant differences between the purely application-level PyTorch simulation and our proposed design flow, highlighting the relevance of circuit-level validation for the design of neural hardware accelerators.}, language = {en} }