@misc{FanGrassKrstic, author = {Fan, X. and Grass, Eckhard and Krstic, Milos}, title = {Aussetzbarer Taktgenerator}, language = {en} } @misc{KrsticFanGrass, author = {Krstic, Milos and Fan, X. and Grass, Eckhard}, title = {GALS Circuit Block and GALS Circuit Device Suitable for Bursty Data Transfer}, language = {en} } @inproceedings{StamenkovićTittelbachHelmrichKrsticetal., author = {Stamenković, Zoran and Tittelbach-Helmrich, Klaus and Krstic, Milos and Perez, J. and Via, J. and Ib{\´a}{\~n}ez, Jes{\´u}s}, title = {Architecture of an Analog Combining MIMO System Compliant to IEEE 802.11a}, language = {en} } @inproceedings{PizKrsticEhrigetal., author = {Piz, M. and Krstic, Milos and Ehrig, Marcus and Grass, Eckhard}, title = {An OFDM Baseband Receiver for Short-Range Communication at 60 GHz}, language = {en} } @article{TroyaChinchillaMaharatnaKrsticetal., author = {Troya Chinchilla, Alfonso Luis and Maharatna, Koushik and Krstic, Milos and Grass, Eckhard and Jagdhold, Ulrich and Kraemer, Rolf}, title = {Efficient Inner Receiver Design for OFDM-Based WLAN Systems: Algorithm and Architecture}, language = {en} } @article{KrsticGrassGuerkaynaketal., author = {Krstic, Milos and Grass, Eckhard and G{\"u}rkaynak, F. and Vivet, P.}, title = {Globally Asynchronous, Locally Synchronous Circuits: Overview \& Outlook}, language = {en} } @inproceedings{MaharatnaTroyaChinchillaKrsticetal., author = {Maharatna, Koushik and Troya Chinchilla, Alfonso Luis and Krstic, Milos and Grass, Eckhard}, title = {On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder}, language = {en} } @inproceedings{GrassHerzelPizetal., author = {Grass, Eckhard and Herzel, F. and Piz, M. and Schmalz, K. and Sun, Yaoming and Glisic, S. and Krstic, Milos and Tittelbach-Helmrich, Klaus and Ehrig, Marcus and Winkler, W. and Scheytt, J. Christoph and Kraemer, Rolf}, title = {60 GHz SiGe-BiCMOS Radio for OFDM Transmission}, language = {en} } @article{KrsticGrassStahletal., author = {Krstic, Milos and Grass, Eckhard and Stahl, C. and Piz, M.}, title = {System Integration by Request-driven GALS Design}, language = {en} } @misc{GrassKrstic, author = {Grass, Eckhard and Krstic, Milos}, title = {Asynchrone H{\"u}llschaltung f{\"u}r eine global asynchrone, lokale synchrone (GALS) Schaltung}, language = {en} } @misc{KrsticGrass, author = {Krstic, Milos and Grass, Eckhard}, title = {GALS-Schaltung mit arbitriertem eingangs- und ausgangsseitigem Taktantrieb}, language = {de} } @inproceedings{KrsticGrass, author = {Krstic, Milos and Grass, Eckhard}, title = {GALSification of IEEE 802.11a Baseband Processor}, language = {en} } @inproceedings{MaharatnaTroyaChinchillaBanerjeeetal., author = {Maharatna, Koushik and Troya Chinchilla, Alfonso Luis and Banerjee, S. and Grass, Eckhard and Krstic, Milos}, title = {A 16-Bit CORDIC Rotator for High-Speed Wireless LAN}, language = {en} } @inproceedings{MaharatnaTroyaChinchillaKrsticetal., author = {Maharatna, Koushik and Troya Chinchilla, Alfonso Luis and Krstic, Milos and Grass, Eckhard and Jagdhold, Ulrich}, title = {A CORDIC Like Processor for Computation of Arctangent and Absolute Magnitude of a Vector}, language = {en} } @article{KrsticMaharatnaTroyaChinchillaetal., author = {Krstic, Milos and Maharatna, Koushik and Troya Chinchilla, Alfonso Luis and Grass, Eckhard and Jagdhold, Ulrich}, title = {Baseband Processor for IEEE 802.11a Standard with embedded BIST}, language = {en} } @inproceedings{KrsticGrass, author = {Krstic, Milos and Grass, Eckhard}, title = {GALS Baseband Processor for WLAN}, language = {en} } @inproceedings{StahlReisigKrstic, author = {Stahl, C. and Reisig, W. and Krstic, Milos}, title = {Hazard Detection in GALS Wrapper: A Case Study}, language = {en} } @article{MaharatnaBanerjeeGrassetal., author = {Maharatna, Koushik and Banerjee, S. and Grass, Eckhard and Krstic, Milos and Troya Chinchilla, Alfonso Luis}, title = {Modified Virtually Scaling Free Adaptive CORDIC Rotator Algorithm and Architecture}, language = {en} } @misc{KrsticStojčevDjordjevicetal., author = {Krstic, Milos and Stojčev, M. K. and Djordjevic, Goran L. and Andrejic, I. D.}, title = {A Mid Value-Select Voter}, series = {Microelectronics Reliability}, volume = {45}, journal = {Microelectronics Reliability}, number = {3/4}, issn = {0026-2714}, doi = {10.1016/j.microrel.2004.07.006}, pages = {733 -- 738}, language = {en} } @inproceedings{KrsticGrassStahl, author = {Krstic, Milos and Grass, Eckhard and Stahl, C.}, title = {Request-Driven GALS Technique for Wireless Communication System}, language = {en} } @techreport{TittelbachHelmrichKrsticFiebigetal., author = {Tittelbach-Helmrich, Klaus and Krstic, Milos and Fiebig, Norbert and Methfessel, Michael}, title = {Test Report for WLAN Access Point Chipset, Deliverable D5.2}, language = {en} } @misc{GrassKrsticWinkler, author = {Grass, Eckhard and Krstic, Milos and Winkler, F.}, title = {GALS-Schaltung und Verfahren zum Betrieb einer GALS-Schaltung}, language = {de} } @inproceedings{GrassWinklerKrsticetal., author = {Grass, Eckhard and Winkler, F. and Krstic, Milos and Julius, A. and Stahl, C. and Piz, M.}, title = {Enhanced GALS Techniques for Datapath Applications}, language = {en} } @inproceedings{KrsticGrass, author = {Krstic, Milos and Grass, Eckhard}, title = {BIST Testing for GALS Systems}, language = {en} } @misc{NikolicDjordjevicKrsticetal., author = {Nikolic, Tatjana and Djordjevic, Goran L. and Krstic, Milos and Stojcev, M.}, title = {Data Transfers over Peripheral Bus Using CDMA Technique}, language = {en} } @inproceedings{FanKrsticWolfetal., author = {Fan, X. and Krstic, Milos and Wolf, Ch. and Grass, Eckhard}, title = {GALS Design for On-Chip Ground Bounce Suppression}, language = {en} } @inproceedings{KrsticFanGrassetal., author = {Krstic, Milos and Fan, X. and Grass, Eckhard and Strano, A. and Bertozzi, Davide and Heer, Ch. and Sanders, B. and Benini, L. and Kakooe, M. R.}, title = {Moonrake Chip - GALS Demonstrator in 40 nm CMOS Technology}, language = {en} } @inproceedings{SimevskiKraemerKrstic, author = {Simevski, Aleksandar and Kraemer, Rolf and Krstic, Milos}, title = {Low-Complexity Integrated Circuit Aging Monitor}, language = {en} } @inproceedings{WolfZeidlerKrsticetal., author = {Wolf, Christoph and Zeidler, Steffen and Krstic, Milos and Kraemer, Rolf}, title = {Overview on ATE Test and Debugging Methods for Asynchronous Circuits}, language = {en} } @inproceedings{SchrapeKrsticPhilippetal., author = {Schrape, Oliver and Krstic, Milos and Philipp, Gunnar and Winkler, Frank}, title = {A Digital Design Flow for Differential ECL High Speed Applications}, language = {en} } @inproceedings{AndjelkovicKrsticKraemer, author = {Andjelkovic, Marko and Krstic, Milos and Kraemer, Rolf}, title = {An Analysis of the Operation and SET Robustness of a CMOS Pulse Stretching Circuit}, series = {20thInternational Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), 19-21 April 2017 Dresden}, booktitle = {20thInternational Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017), 19-21 April 2017 Dresden}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5386-0472-4}, pages = {6}, language = {en} } @inproceedings{AndjelkovicIlicStamenkovićetal., author = {Andjelkovic, Marko and Ilic, Aleksandar and Stamenković, Zoran and Krstic, Milos and Kraemer, Rolf}, title = {An Overview of the Current Models for the Circuit-level Simulations of Single Event Transients}, series = {Book of abstracts, 5th International Conference on Radiation and Applications in Various Fields of Research (RAD 2017), June 12-16, 2017, Budva, Montenegro}, booktitle = {Book of abstracts, 5th International Conference on Radiation and Applications in Various Fields of Research (RAD 2017), June 12-16, 2017, Budva, Montenegro}, pages = {S. 184}, language = {en} } @inproceedings{AndjelkovicIlicStamenkovićetal., author = {Andjelkovic, Marko and Ilic, Aleksandar and Stamenković, Zoran and Krstic, Milos and Kraemer, Rolf}, title = {An Overview of the Modeling and Simulation of the Single Event Transients at the Circuit Level}, series = {30th International Conference on Microelectronics (MIEL), 9-11 Oct. 2017, Nis, Serbia}, booktitle = {30th International Conference on Microelectronics (MIEL), 9-11 Oct. 2017, Nis, Serbia}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5386-2563-7}, doi = {10.1109/MIEL.2017.8190065}, pages = {35 -- 44}, language = {en} } @inproceedings{AndjelkovicKrsticKraemer, author = {Andjelkovic, Marko and Krstic, Milos and Kraemer, Rolf}, title = {Assessment of the Amplitude-duration Criterion for SET Robusness Evaluation}, series = {23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, Greece, 3-5 July 2017}, booktitle = {23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, Greece, 3-5 July 2017}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5386-0352-9}, language = {en} } @inproceedings{SimevskiSchleisiekPetrovicetal., author = {Simevski, Aleksandar and Schleisiek, Klaus and Petrovic, Vladimir and Beller, Norbert and Skoncej, Patryk and Schoof, Gunther and Krstic, Milos}, title = {Implementation of a Real Time Unit for Satellite Applications}, series = {19th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS), 20-22 April 2016, Kosice, Slovakia}, booktitle = {19th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS), 20-22 April 2016, Kosice, Slovakia}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5090-2467-4}, pages = {180}, language = {en} } @inproceedings{KrsticFanBabicetal., author = {Krstic, Milos and Fan, Xin and Babic, Milan and Grass, Eckhard and Bjerregaard, T. and Yakovlev, A.}, title = {Reducing Switching Noise Effects by Advanced Clock Management}, series = {11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo), 4-8 July, St. Petersburg, Russia 2017}, booktitle = {11th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo), 4-8 July, St. Petersburg, Russia 2017}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5386-2689-4}, pages = {3 -- 8}, language = {en} } @inproceedings{BabicZeidlerKrstic, author = {Babic, Milan and Zeidler, Steffen and Krstic, Milos}, title = {GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits}, series = {22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2016), 8-11 May, Porto Alegre, Brazil, 2016}, booktitle = {22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2016), 8-11 May, Porto Alegre, Brazil, 2016}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-4673-9007-1}, pages = {67 -- 74}, language = {en} } @inproceedings{AndjelkovicPetrovicNenadovicetal., author = {Andjelkovic, Marko and Petrovic, Vladimir and Nenadovic, Miljana and Breitenreiter, Anselm and Krstic, Milos and Kraemer, Rolf}, title = {Design of an On-Chip System for the SET Pulse Width Measurement}, series = {Euromicro Conference on Digital System Design, 30 Aug.-1 Sept., Vienna, Austria 2017}, booktitle = {Euromicro Conference on Digital System Design, 30 Aug.-1 Sept., Vienna, Austria 2017}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5386-2146-2}, pages = {111 -- 118}, language = {en} } @inproceedings{AndjelkovicKrsticKraemeretal., author = {Andjelkovic, Marko and Krstic, Milos and Kraemer, Rolf and Veeravalli, Varadan Savulimedu and Steininger, Andreas}, title = {Erstellung eines Modells der kritischen Ladung zur Bewertung der Robustheit gegen{\"u}ber SETs und SEUs: Fallstudie Muller C-Element}, series = {Zuverl{\"a}ssigkeit und Entwurf, 9. ITG/GMM/GI-Fachtagung vom 18.-20. September 2017 in Cottbus}, booktitle = {Zuverl{\"a}ssigkeit und Entwurf, 9. ITG/GMM/GI-Fachtagung vom 18.-20. September 2017 in Cottbus}, publisher = {Berlin}, address = {VDE Verlag}, isbn = {978-3-8007-4444-2}, pages = {17 -- 24}, language = {de} } @inproceedings{AndjelkovicNenadovicPetrovicetal., author = {Andjelkovic, Marko and Nenadovic, Miljana and Petrovic, Vladimir and Krstic, Milos and Kraemer, Rolf}, title = {Evaluation of the Pulse Stretcher for Detection of Very Short Single Event Transients}, series = {Book of abstracts, 5th International Conference on Radiation and Applications in Various Fields of Research (RAD 2017), Budva, Montenegro, 2017}, booktitle = {Book of abstracts, 5th International Conference on Radiation and Applications in Various Fields of Research (RAD 2017), Budva, Montenegro, 2017}, pages = {S. 214}, language = {en} } @inproceedings{AndjelkovicKrsticKraemer, author = {Andjelkovic, Marko and Krstic, Milos and Kraemer, Rolf}, title = {Comparison of the SET Sensitivity of Standard Logic Gates Designed in 130 nm CMOS Technology}, series = {30th International Conference on Microelectronics (MIEL), 9-11 Oct. 2017, Nis, Serbia}, booktitle = {30th International Conference on Microelectronics (MIEL), 9-11 Oct. 2017, Nis, Serbia}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5386-2563-7}, doi = {10.1109/MIEL.2017.8190106}, pages = {217 -- 220}, language = {en} } @inproceedings{AndjelkovicJagdholdKrsticetal., author = {Andjelkovic, Marko and Jagdhold, Ulrich and Krstic, Milos and Kraemer, Rolf}, title = {2D TCAD Simulation of Single Event Transients in 250 nm Bulk CMOS Technology}, series = {Zuverl{\"a}ssigkeit und Entwurf, 9. ITG/GMM/GI-Fachtagung vom 18.-20. September 2017 in Cottbus}, booktitle = {Zuverl{\"a}ssigkeit und Entwurf, 9. ITG/GMM/GI-Fachtagung vom 18.-20. September 2017 in Cottbus}, publisher = {Berlin}, address = {VDE Verlag}, isbn = {978-3-8007-4444-2}, pages = {90 -- 96}, language = {en} } @inproceedings{BabicKrstic, author = {Babic, Milan and Krstic, Milos}, title = {A Substrate Noise Reduction Methodology Based on Power Domain Separation of GALS Subcomponents}, series = {27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), September 25-27, 2017, Aristotle University Research Dissemination Center (KEDEA), Thessaloniki, Greece}, booktitle = {27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), September 25-27, 2017, Aristotle University Research Dissemination Center (KEDEA), Thessaloniki, Greece}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5090-6462-5}, doi = {10.1109/PATMOS.2017.8106981}, pages = {6}, language = {en} } @inproceedings{BabicKrstic, author = {Babic, Milan and Krstic, Milos}, title = {GALS Methodology for Substrate Noise Reduction in BiCMOS Technologies}, series = {Proceedings, Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN), Tallinn, Estonia, 2015}, booktitle = {Proceedings, Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN), Tallinn, Estonia, 2015}, pages = {2}, language = {en} } @inproceedings{BabicKrstic, author = {Babic, Milan and Krstic, Milos}, title = {A Coarse Model for Estimation of Switching Noise Coupling in Lightly Doped Substrates}, series = {18th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Belgrade, Serbia, 2015}, booktitle = {18th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Belgrade, Serbia, 2015}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-4799-6780-3}, pages = {217 -- 222}, language = {en} } @inproceedings{BabicFanKrstic, author = {Babic, Milan and Fan, Xin and Krstic, Milos}, title = {Frequency-Domain Modeling of Ground Bounce and Substrate Noise for Synchronous and GALS Systems}, series = {25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 1-4 Sept. Salvador, Brazil 2015}, booktitle = {25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 1-4 Sept. Salvador, Brazil 2015}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-4673-9419-2}, pages = {126 -- 132}, language = {en} } @inproceedings{AndjelkovicKrsticKraemeretal., author = {Andjelkovic, Marko and Krstic, Milos and Kraemer, Rolf and Veeravalli, Varadan Savulimedu and Steininger, Andreas}, title = {A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study}, series = {IEEE 26th Asian Test Symposium (ATS), Taipei, Taiwan, 28-30 November 2017}, booktitle = {IEEE 26th Asian Test Symposium (ATS), Taipei, Taiwan, 28-30 November 2017}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5386-2437-1}, doi = {10.1109/ATS.2017.27}, pages = {78 -- 83}, language = {en} } @inproceedings{AndjelkovicStamenkovićKrsticetal., author = {Andjelkovic, Marko and Stamenković, Zoran and Krstic, Milos and Kraemer, Rolf}, title = {Impact of Resistive Open and Bridge Defects on the SET Robustness of CMOS Combinational Logic}, series = {IEEE East-West Design \& Test Symposium (EWDTS 2018), Kazan, Russia, 14 - 17 September 2018}, booktitle = {IEEE East-West Design \& Test Symposium (EWDTS 2018), Kazan, Russia, 14 - 17 September 2018}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5386-5709-6}, doi = {10.1109/EWDTS.2018.8524748}, pages = {6}, language = {en} } @misc{AndjelkovicKrsticKraemer, author = {Andjelkovic, Marko and Krstic, Milos and Kraemer, Rolf}, title = {Study of the Operation and SET Robustness of a CMOS Pulse Stretching Circuit}, series = {Microelectronics Reliability}, volume = {82}, journal = {Microelectronics Reliability}, issn = {0026-2714}, doi = {10.1016/j.microrel.2017.12.022}, pages = {100 -- 112}, language = {en} } @inproceedings{AndjelkovicBabicLietal., author = {Andjelkovic, Marko and Babic, Milan and Li, Yuanqing and Schrape, Oliver and Krstic, Milos and Kraemer, Rolf}, title = {Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational Gates}, series = {25th IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), Bordeaux, France, 09 - 12 December 2018}, booktitle = {25th IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), Bordeaux, France, 09 - 12 December 2018}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-5386-9562-3}, doi = {10.1109/ICECS.2018.8617996}, pages = {361 -- 364}, language = {en} } @misc{SegabinazziFerreiraGeorgeChenetal., author = {Segabinazzi Ferreira, Raphael and George, Nevin and Chen, Junchao and H{\"u}bner, Michael and Krstic, Milos and Nolte, J{\"o}rg and Vierhaus, Heinrich Theodor}, title = {Configurable Fault Tolerant Circuits and System Level Integration for Self-Awareness}, series = {Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design}, journal = {Proceedings of the Work in Progress Session held in connection with SEAA 2019, the 45th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2019, the 22nd EUROMICRO Conference on Digital System Design}, publisher = {SEA-Publications}, address = {Kallithea, Chalkidiki (Greece)}, isbn = {978-3-902457-54-7}, doi = {10.26127/BTUOpen-5050}, pages = {2}, abstract = {Scaling minimum features of ICs down to the 10nm- area and below has allowed high integration rates in electronics. Scaling at supply voltages of 1V and below also implies a rising level of stress which drives aging effects that reduce switching speed and the expected life time. Additionally, vulnerability from particle radiation is increased. Hence, fault detection and on- line correction become a must for many applications. However, not only fault tolerance but self-awareness becomes also an advantage. Provided that by being aware of its own healthy state allow optimized configurations regarding system operation modes and configurable hardware mechanism. This paper shows a preliminary work in a configurable circuit and explores its configuration possibilities when integrated into a complete system.}, language = {en} } @misc{AndjelkovicLiStamenkovićetal., author = {Andjelkovic, Marko and Li, Yuanqing and Stamenković, Zoran and Krstic, Milos and Kraemer, Rolf}, title = {Characterization and Modeling of SET Generation Effects in CMOS Standard Logic Cells}, series = {25th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2019), Rhodos, Greece, 01 - 03 July 2019}, journal = {25th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2019), Rhodos, Greece, 01 - 03 July 2019}, publisher = {IEEE}, isbn = {978-1-7281-2490-2}, issn = {1942-9401}, doi = {10.1109/IOLTS.2019.8854379}, pages = {4}, language = {en} } @misc{VeleskiKraemerKrstic, author = {Veleski, Mitko and Kraemer, Rolf and Krstic, Milos}, title = {SWIELD: An In Situ Approach for Adaptive Low Power and Error-Resilient Operation}, series = {17th IEEE East-West Design \& Test Symposium (EWDTS 2019), Batumi, Georgia, 13 - 16 September 2019}, journal = {17th IEEE East-West Design \& Test Symposium (EWDTS 2019), Batumi, Georgia, 13 - 16 September 2019}, publisher = {IEEE}, isbn = {978-1-7281-1003-5}, issn = {2472-761X}, doi = {10.1109/EWDTS.2019.8884428}, pages = {6}, language = {en} } @misc{JenihhinHamdiouiSonzaReordaetal., author = {Jenihhin, Maksim and Hamdioui, Said and Sonza-Reorda, Matteo and Krstic, Milos and Langend{\"o}rfer, Peter and Sauer, Christian and Klotz, Anton and H{\"u}bner, Michael and Nolte, J{\"o}rg and Vierhaus, Heinrich Theodor and Selimis, Georgions and Alexandrescu, Dan and Taouil, Mottaqiallah and Schrijen, Geert-Jan and Sterpone, Luca and Squillero, Giovanni and Dyka, Zoya and Raik, Jaan}, title = {RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems}, series = {ArXiv.org}, journal = {ArXiv.org}, pages = {7}, language = {en} } @misc{VeleskiKraemerKrstic, author = {Veleski, Mitko and Kraemer, Rolf and Krstic, Milos}, title = {A Programmable Error-Predictive In-Situ Delay Monitor for Adaptive Low Power and Error-Resilient Complex System-On-Chip}, series = {9th Biannual European - Latin American Summer School on Design, Test and Reliability (BELAS 2019), Frankfurt/Oder}, journal = {9th Biannual European - Latin American Summer School on Design, Test and Reliability (BELAS 2019), Frankfurt/Oder}, language = {en} } @misc{VeleskiKraemerKrstic, author = {Veleski, Mitko and Kraemer, Rolf and Krstic, Milos}, title = {Programmable In-Situ Delay Monitor for Energy-Efficient and Resilient Complex SoC}, series = {Proc. 24th IEEE European Test Symposium: PhD Forum (ETS 2019)}, journal = {Proc. 24th IEEE European Test Symposium: PhD Forum (ETS 2019)}, language = {en} } @misc{VeleskiKraemerKrstic, author = {Veleski, Mitko and Kraemer, Rolf and Krstic, Milos}, title = {The Effects of Voltage Scaling on Reliability and Power Consumption in Multiprocessor Systems}, series = {Proc. 30. GI/GMM/ITG-Workshop Testmethoden und Zuverl{\"a}ssigkeit von Schaltungen und Systemen (TuZ 2018), 38 (2018)}, journal = {Proc. 30. GI/GMM/ITG-Workshop Testmethoden und Zuverl{\"a}ssigkeit von Schaltungen und Systemen (TuZ 2018), 38 (2018)}, language = {en} } @misc{VeleskiKraemerKrstic, author = {Veleski, Mitko and Kraemer, Rolf and Krstic, Milos}, title = {An Overview of Cross-Layer Resilience Design Methods}, series = {RESCUE 2017, Limassol}, journal = {RESCUE 2017, Limassol}, pages = {4}, language = {en} } @misc{AndjelkovicVeleskiChenetal., author = {Andjelkovic, Marko and Veleski, Mitko and Chen, Junchao and Simevski, Aleksandar and Krstic, Milos}, title = {A Particle Detector Based on Pulse Stretching Inverter Chain}, series = {26th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2019), Genova}, journal = {26th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2019), Genova}, isbn = {978-1-7281-0996-1}, doi = {10.1109/ICECS46596.2019.8964644}, pages = {4}, language = {en} } @misc{AndjelkovicChenSimevskietal., author = {Andjelkovic, Marko and Chen, Junchao and Simevski, Aleksandar and Stamenkovic, Zoran and Krstic, Milos and Kraemer, Rolf}, title = {A Review of Particle Detectors for Space-Borne Self-Adaptive Fault Tolerant Systems}, series = {18th IEEE East-West Design and Test Symposium (EWDTS 2020), Varna, Bulgaria, 04 - 07 September 2020}, journal = {18th IEEE East-West Design and Test Symposium (EWDTS 2020), Varna, Bulgaria, 04 - 07 September 2020}, publisher = {IEEE}, isbn = {978-1-7281-9899-6}, issn = {2472-761X}, doi = {10.1109/EWDTS50664.2020.9225138}, language = {en} } @misc{VeleskiHuebnerKrsticetal., author = {Veleski, Mitko and H{\"u}bner, Michael and Krstic, Milos and Kraemer, Rolf}, title = {Highly Configurable Framework for Adaptive Low Power and Error-Resilient System-On-Chip}, series = {23rd EUROMICRO Conference on Digital System Design (DSD 2020), Portoroz, Slovenia, 26 - 28 August 2020}, journal = {23rd EUROMICRO Conference on Digital System Design (DSD 2020), Portoroz, Slovenia, 26 - 28 August 2020}, publisher = {IEEE}, isbn = {978-1-7281-9535-3}, doi = {10.1109/DSD51259.2020.00015}, pages = {24 -- 28}, language = {en} } @misc{WenBaroniPerezetal., author = {Wen, Jianan and Baroni, Andrea and P{\´e}rez, Eduardo and Ulbricht, Markus and Wenger, Christian and Krstic, Milos}, title = {Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages}, series = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, journal = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, isbn = {978-1-6654-5938-9}, issn = {2765-933X}, doi = {10.1109/DFT56152.2022.9962345}, pages = {1 -- 6}, abstract = {RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states.}, language = {en} } @misc{VeleskiHuebnerKrsticetal., author = {Veleski, Mitko and H{\"u}bner, Michael and Krstic, Milos and Kraemer, Rolf}, title = {Design and implementation strategy of adaptive processor-based systems for error resilient and power-efficient operation}, series = {24th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems, DDECS, April 7-9 2021}, journal = {24th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems, DDECS, April 7-9 2021}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-6654-3595-6}, doi = {10.1109/DDECS52668.2021.9417023}, pages = {57 -- 62}, language = {en} } @misc{VeleskiHuebnerKrsticetal., author = {Veleski, Mitko and H{\"u}bner, Michael and Krstic, Milos and Kraemer, Rolf}, title = {Towards Error Resilient and Power-Efficient Adaptive Multiprocessor System using Highly Configurable and Flexible Cross-Layer Framework}, series = {IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), IOLTS 2021, June 28-30, 2021}, journal = {IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), IOLTS 2021, June 28-30, 2021}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-6654-3370-9}, doi = {10.1109/IOLTS52814.2021.9486695}, pages = {1 -- 7}, language = {en} } @inproceedings{WenVargasZhuetal., author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and P{\´e}rez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos}, title = {Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment}, series = {2024 IEEE 25th Latin American Test Symposium (LATS)}, booktitle = {2024 IEEE 25th Latin American Test Symposium (LATS)}, publisher = {IEEE}, doi = {10.1109/LATS62223.2024.10534601}, pages = {6}, abstract = {Emerging device technologies such as resistive RAM (RRAM) are increasingly recognized in enhancing system performance, particularly in applications demanding extensive vector-matrix multiplications (VMMs) with high parallelism. However, a significant limitation in current electronics design automation (EDA) tools is their lack of support for rapid prototyping, design space exploration, and the integration of inherent process-dependent device variability into system-level simulations, which is essential for assessing system reliability. To address this gap, we introduce a field-programmable gate array (FPGA) based emulation approach for RRAM crossbars featuring cycle-accurate emulations in real time without relying on complex device models. Our approach is based on pre-generated look-up tables (LUTs) to accurately represent the RRAM device behavior. To efficiently model the device variability at the system level, we propose using the multivariate kernel density estimation (KDE) method to augment the measured RRAM data. The proposed emulator allows precise latency determination for matrix mapping and computation operations. Meanwhile, by coupling with the NeuroSim framework, the corresponding energy consumption can be estimated. In addition to facilitating a range of in-depth system assessments, experimental results suggest a remarkable reduction of emulation time compared to the classic behavioral simulation.}, language = {en} } @misc{FritscherSinghRizzietal., author = {Fritscher, Markus and Singh, Simranjeet and Rizzi, Tommaso and Baroni, Andrea and Reiser, Daniel and Mallah, Maen and Hartmann, David and Bende, Ankit and Kempen, Tim and Uhlmann, Max and Kahmen, Gerhard and Fey, Dietmar and Rana, Vikas and Menzel, Stephan and Reichenbach, Marc and Krstic, Milos and Merchant, Farhad and Wenger, Christian}, title = {A flexible and fast digital twin for RRAM systems applied for training resilient neural networks}, series = {Scientific Reports}, volume = {14}, journal = {Scientific Reports}, number = {1}, publisher = {Springer Science and Business Media LLC}, issn = {2045-2322}, doi = {10.1038/s41598-024-73439-z}, pages = {13}, abstract = {Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the "ideal memristor" which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a "push button" modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).}, language = {en} } @misc{FritscherWengerKrstic, author = {Fritscher, Markus and Wenger, Christian and Krstic, Milos}, title = {From device to application - integrating RRAM Accelerator Blocks into large AI systems}, series = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, journal = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, publisher = {IEEE}, isbn = {979-8-3503-5411-9}, issn = {2159-3477}, doi = {10.1109/ISVLSI61997.2024.00111}, pages = {592 -- 592}, abstract = {This work provides an introduction to design methodologies for RRAM-based systems. We illustrate the impact of device variation on the performance of neural networks and propose a circuit-level integration approach for RRAM-based compute blocks. Moreover, we demonstrate a possible architectural integration by incorporating RRAM-based VMM blocks fabricated in a 130 nm CMOS process into a RISC-V.}, language = {en} } @misc{FritscherUhlmannOstrovskyyetal., author = {Fritscher, Markus and Uhlmann, Max and Ostrovskyy, Philip and Reiser, Daniel and Chen, Junchao and Schubert, Andreas and Schulze, Carsten and Kahmen, Gerhard and Fey, Dietmar and Reichenbach, Marc and Krstic, Milos and Wenger, Christian}, title = {Area-efficient digital design using RRAM-CMOS standard cells}, series = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, volume = {18}, journal = {2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, publisher = {IEEE}, isbn = {979-8-3503-5411-9}, issn = {2159-3477}, doi = {10.1109/ISVLSI61997.2024.00026}, pages = {81 -- 87}, abstract = {Extending the scalability of digital integrated circuits through novel device concepts is an attractive option. Among these concepts, resistive random access memory (RRAM) devices allow fast and nonvolatile operation. However, building large memristive systems is still challenging since large analog circuits have to be designed and integrated. In this paper, we propose a novel solution - the implementation of digital standard cells by the means of RRAM devices. While this methodology is universal, with applications ranging from few-device-circuits to large macroblocks, we demonstrate it for a 2T2R-cell. The benefits of using RRAM devices are demonstrated by implementing a NAND standard cell merely consuming the area of two transistors. This cell is about 25 \% smaller than the equivalent CMOS NAND in the same technology. We use these cells to implement a half adder, beating the area of the equivalent CMOS implementation using more sophisticates gates by 15 \%. Lastly, we fully integrate this novel standard cell into a digital standard cell library and perform a synthesis and layout of a RISC-V CPU core.}, language = {en} } @misc{WenBaroniPerezetal., author = {Wen, Jianan and Baroni, Andrea and Perez, Eduardo and Uhlmann, Max and Fritscher, Markus and KrishneGowda, Karthik and Ulbricht, Markus and Wenger, Christian and Krstic, Milos}, title = {Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator}, series = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, journal = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, publisher = {IEEE}, isbn = {978-3-9819263-8-5}, issn = {1558-1101}, doi = {10.23919/DATE58400.2024.10546709}, pages = {1 -- 6}, abstract = {The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 \% and 18 \%, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83\% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero.}, language = {en} } @misc{PerezBoschQuesadaMahadevaiahRizzietal., author = {Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Rizzi, Tommaso and Wen, Jianan and Ulbricht, Markus and Krstic, Milos and Wenger, Christian and P{\´e}rez, Eduardo}, title = {Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing}, series = {IEEE Transactions on Electron Devices}, volume = {70}, journal = {IEEE Transactions on Electron Devices}, number = {4}, issn = {0018-9383}, doi = {10.1109/TED.2023.3244509}, pages = {2009 -- 2014}, abstract = {Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices' nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.}, language = {en} } @misc{DykaKabinBrzozowskietal., author = {Dyka, Zoya and Kabin, Ievgen and Brzozowski, Marcin and Panic, Goran and Calligaro, Cristiano and Krstic, Milos and Langend{\"o}rfer, Peter}, title = {On the SCA Resistance of Crypto IP Cores}, series = {23rd IEEE Latin-American Test Symposium (LATS 2022), Montevideo, Uruguay, 05-08 September 2022}, journal = {23rd IEEE Latin-American Test Symposium (LATS 2022), Montevideo, Uruguay, 05-08 September 2022}, isbn = {978-1-6654-5707-1}, issn = {2373-0862}, doi = {10.1109/LATS57337.2022.9937007}, pages = {2}, language = {en} } @misc{WenVargasZhuetal., author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and Perez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos}, title = {RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation}, series = {Microelectronics Reliability}, volume = {168}, journal = {Microelectronics Reliability}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {0026-2714}, doi = {10.1016/j.microrel.2025.115630}, pages = {1 -- 10}, abstract = {The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current-voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector-matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments.}, language = {en} } @misc{FritscherUhlmannOstrovskyyetal., author = {Fritscher, Markus and Uhlmann, Max and Ostrovskyy, Philip and Reiser, Daniel and Chen, Junchao and Wen, Jianan and Schulze, Carsten and Kahmen, Gerhard and Fey, Dietmar and Reichenbach, Marc and Krstic, Milos and Wenger, Christian}, title = {RISC-V CPU design using RRAM-CMOS standard cells}, series = {IEEE transactions on very large scale integration (VLSI) systems}, journal = {IEEE transactions on very large scale integration (VLSI) systems}, editor = {Wenger, Christian}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1063-8210}, doi = {10.1109/TVLSI.2025.3554476}, pages = {1 -- 9}, abstract = {The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25\% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7\% smaller area than the equivalent design using standard CMOS gates.}, language = {en} } @misc{DykaKabinBrzozowskietal., author = {Dyka, Zoya and Kabin, Ievgen and Brzozowski, Marcin and Panic, Goran and Calligaro, Cristiano and Krstic, Milos and Langendoerfer, Peter}, title = {On the influence of cell libraries and other parameters to SCA resistance of crypto IP cores}, series = {2024 13th Mediterranean Conference on Embedded Computing (MECO)}, journal = {2024 13th Mediterranean Conference on Embedded Computing (MECO)}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3503-8756-8}, doi = {10.1109/MECO62516.2024.10577776}, pages = {1 -- 5}, abstract = {The ever-growing complexity of modern systems as well as the shrinking time to market enforces the use of already designed hardware components i.e. hard and soft IP cores. The fact that also requirements with respect to security significantly increased and that side-channel analysis (SCA) attacks are meanwhile a well-known threat it is paramount to ensure SCA resistance of ASICs and FPGA implementations derived from cryptographic IP cores. This requires to evaluate this feature for each IP core and target technology even down to the level of the cell library. The experiments reported here clearly show that the three available cell libraries even though developed for the same 130nm technology of IHP exhibit different sensitivity to SCA attacks ranging from quite resistant to very vulnerable.}, language = {en} } @misc{WenBaroniUhlmannetal., author = {Wen, Jianan and Baroni, Andrea and Uhlmann, Max and Perez, Eduardo and Wenger, Christian and Krstic, Milos}, title = {ReFFT : an energy-efficient RRAM-based FFT accelerator}, series = {IEEE transactions on computer-aided design of integrated circuits and systems}, journal = {IEEE transactions on computer-aided design of integrated circuits and systems}, publisher = {IEEE}, address = {Piscataway, NJ}, issn = {0278-0070}, doi = {10.1109/TCAD.2025.3627146}, pages = {1 -- 14}, abstract = {The fast Fourier transform (FFT) is a highly efficient algorithm for computing the discrete Fourier transform (DFT). It is widely employed in various applications, including digital communication, image processing, and signal analysis. Recently, in-memory computing architectures based on emerging technologies, such as resistive RAM (RRAM), have demonstrated promising performance with low hardware cost for data-intensive applications. However, directly mapping FFT onto RRAM crossbars is challenging because the algorithm relies on many small, sequential butterfly operations, while cross-bars are optimized for large-scale, highly parallel vector-matrix multiplications (VMMs). In this paper, we introduce ReFFT, a system architecture that reformulates FFT computations for efficient execution on RRAM crossbars. ReFFT combines the reduced computational complexity of FFT with the parallel VMM capability of RRAM. We incorporate measured device data into our framework to analyze the effect of variability and develop an adaptive mapping scheme that improves twiddle-factor programming accuracy, leading to a 9.9 dB peak signal-to-noise ratio (PSNR) improvement for a 256-point FFT. Compared with prior RRAM-based DFT designs, ReFFT achieves up to 4.6× and 19.5× higher energy efficiency for 256- and 2048-point FFTs, respectively. The system is further validated in digital communication and satellite image compression tasks.}, language = {en} } @misc{WenBaroniMistronietal., author = {Wen, Jianan and Baroni, Andrea and Mistroni, Alberto and Perez, Eduardo and Zambelli, Cristian and Wenger, Christian and Krstic, Milos and Bolzani P{\"o}hls, Leticia Maria}, title = {ReDiM : an efficient strategy for read disturb mitigation in RRAM-based accelerators}, series = {2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)}, journal = {2025 IEEE 31st International Symposium on On-Line Testing and Robust System Design (IOLTS)}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {979-8-3315-3334-2}, doi = {10.1109/IOLTS65288.2025.11117065}, pages = {1 -- 7}, abstract = {Resistive RAM (RRAM) has emerged as a promising non-volatile memory technology for implementing energy-efficient hardware accelerators within the in-memory computing (IMC) paradigm. However, due to the immature fabrication process and inherent material instabilities, frequent read operations during computations can induce read disturb effects, leading to unintended resistance drift and potential data corruption. Existing mitigation approaches primarily focus on detecting read disturb effects and triggering memory refresh operations. In this work, we propose an architecture-level solution that mitigates read disturb in RRAM-based accelerators. Our strategy employs crossbar duplication and decomposes the single high input pulse into two lower-amplitude pulses, effectively minimizing the risk of read disturb. To validate our approach, we develop a simulation framework that incorporates measurement data from characterized RRAM devices under read disturb stress conditions. Experimental results on VGG-8 with CIFAR-10 demonstrate that the proposed method significantly mitigates inference accuracy degradation caused by read disturb in RRAM-based accelerators, while incurring modest area and energy overheads of 12.32\% and 2.15\%, respectively. This work provides a practical and scalable solution for enhancing the robustness of RRAM-based accelerators in edge and high-performance computing applications.}, language = {en} }