@misc{WenBaroniPerezetal., author = {Wen, Jianan and Baroni, Andrea and Perez, Eduardo and Uhlmann, Max and Fritscher, Markus and KrishneGowda, Karthik and Ulbricht, Markus and Wenger, Christian and Krstic, Milos}, title = {Towards reliable and energy-efficient RRAM based discrete fourier transform accelerator}, series = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, journal = {2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)}, publisher = {IEEE}, isbn = {978-3-9819263-8-5}, issn = {1558-1101}, doi = {10.23919/DATE58400.2024.10546709}, pages = {1 -- 6}, abstract = {The Discrete Fourier Transform (DFT) holds a prominent place in the field of signal processing. The development of DFT accelerators in edge devices requires high energy efficiency due to the limited battery capacity. In this context, emerging devices such as resistive RAM (RRAM) provide a promising solution. They enable the design of high-density crossbar arrays and facilitate massively parallel and in situ computations within memory. However, the reliability and performance of the RRAM-based systems are compromised by the device non-idealities, especially when executing DFT computations that demand high precision. In this paper, we propose a novel adaptive variability-aware crossbar mapping scheme to address the computational errors caused by the device variability. To quantitatively assess the impact of variability in a communication scenario, we implemented an end-to-end simulation framework integrating the modulation and demodulation schemes. When combining the presented mapping scheme with an optimized architecture to compute DFT and inverse DFT(IDFT), compared to the state-of-the-art architecture, our simulation results demonstrate energy and area savings of up to 57 \% and 18 \%, respectively. Meanwhile, the DFT matrix mapping error is reduced by 83\% compared to conventional mapping. In a case study involving 16-quadrature amplitude modulation (QAM), with the optimized architecture prioritizing energy efficiency, we observed a bit error rate (BER) reduction from 1.6e-2 to 7.3e-5. As for the conventional architecture, the BER is optimized from 2.9e-3 to zero.}, language = {en} } @inproceedings{UlbrichtSchoelzelKoaletal., author = {Ulbricht, Markus and Sch{\"o}lzel, Mario and Koal, Tobias and Vierhaus, Heinrich Theodor}, title = {A New Hierarchical Built-In Test with On-Chip Diagnosis for VLIW Processors}, series = {IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS 2011), Cottbus, Germany, 13 - 15 April 2011}, booktitle = {IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS 2011), Cottbus, Germany, 13 - 15 April 2011}, isbn = {978-1-4244-9755-3}, pages = {143 -- 146}, abstract = {Tagungsbeitrag DDECS 2011, Cottbus}, language = {en} } @inproceedings{UlbrichtSchoelzelKoaletal., author = {Ulbricht, Markus and Sch{\"o}lzel, Mario and Koal, Tobias and Vierhaus, Heinrich Theodor}, title = {A New Hiararchical Built-In SElf Test with On-Chip Diagnosis for VLIW Processors}, abstract = {Tagungsbeitrag 23. ITG-Tagung "Test und Zuverl{\"a}ssigeit von Schaltungen und Systemen", Passau, 2011}, language = {en} } @inproceedings{KoalUlbrichtEngelkeetal., author = {Koal, Tobias and Ulbricht, Markus and Engelke, Piet and Vierhaus, Heinrich Theodor}, title = {Logic Self Repair Architecture with Self Test Capabilities}, series = {Zuverl{\"a}ssigkeit und Entwurf, 6. GMM/GI/ITG-Fachtagung vom 25. bis 27. September 2012 in Bremen}, booktitle = {Zuverl{\"a}ssigkeit und Entwurf, 6. GMM/GI/ITG-Fachtagung vom 25. bis 27. September 2012 in Bremen}, editor = {Drechsler, Rolf}, publisher = {VDE-Verl.}, address = {Berlin [u.a.]}, isbn = {978-3-8007-3445-0}, language = {en} } @inproceedings{KoalUlbrichtEngelkeetal., author = {Koal, Tobias and Ulbricht, Markus and Engelke, Piet and Vierhaus, Heinrich Theodor}, title = {Selbstreparatur f{\"u}r Logik-Baugruppen mit erweiterten F{\"a}higkeiten f{\"u}r die Kompensation von Fertigungsfehlern und Fr{\"u}hausf{\"a}llen}, series = {Dresdner Arbeitstagung f{\"u}r Schaltungs- und Systementwurf (DASS), Dresden, Mai 2012, Tagungsband}, booktitle = {Dresdner Arbeitstagung f{\"u}r Schaltungs- und Systementwurf (DASS), Dresden, Mai 2012, Tagungsband}, publisher = {Fraunhofer IIS, Institutsteil EAS [u.a.]}, address = {Dresden}, isbn = {978-3-8396-0404-5}, language = {de} } @inproceedings{UlbrichtKoalVierhaus, author = {Ulbricht, Markus and Koal, Tobias and Vierhaus, Heinrich Theodor}, title = {Activity Migration in M-of-N-Systems by Means of Loading-Balancing}, series = {15th Euromicro Conference on Digital Systems Design (DSD), September 2012}, booktitle = {15th Euromicro Conference on Digital Systems Design (DSD), September 2012}, publisher = {IEEE}, address = {Piscataway}, isbn = {978-1-4673-2498-4}, pages = {258 -- 263}, language = {en} } @inproceedings{KoalUlbrichtEngelkeetal., author = {Koal, Tobias and Ulbricht, Markus and Engelke, Piet and Vierhaus, Heinrich Theodor}, title = {On the Feasibility of Combining On-Line-Test and Self Repair for Logic Circuits}, series = {16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2013), Karlovny Vary, April 2013}, booktitle = {16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2013), Karlovny Vary, April 2013}, editor = {Sekanina, Lukas}, publisher = {IEEE Computer Society}, isbn = {978-1-4673-6135-4}, language = {en} } @inproceedings{KoalUlbrichtEngelkeetal., author = {Koal, Tobias and Ulbricht, Markus and Engelke, Piet and Vierhaus, Heinrich Theodor}, title = {On-Line-Test, Fehlerkorrektur znd Selbstreparatur mit Time-Shared TMR}, series = {Tagungsband Dresdner Arbeitstagung f{\"u}r Schaltungs- und Systementwurf (DASS), April 2013}, booktitle = {Tagungsband Dresdner Arbeitstagung f{\"u}r Schaltungs- und Systementwurf (DASS), April 2013}, editor = {Dietrich, Manfred}, publisher = {Fraunhofer-Verl.}, address = {Stuttgart}, isbn = {978-3-8396-0545-5}, language = {de} } @inproceedings{KoalUlbrichtVierhaus, author = {Koal, Tobias and Ulbricht, Markus and Vierhaus, Heinrich Theodor}, title = {Virtual TMR Schemes Combining Fault Tolerance and Self Repair}, series = {16th IEEE International Euromicro Conference on Digital System Design, DSD 2013, 4-6 Sep 2013, Santander, Spain}, booktitle = {16th IEEE International Euromicro Conference on Digital System Design, DSD 2013, 4-6 Sep 2013, Santander, Spain}, publisher = {IEEE}, isbn = {978-0-7695-5074-9}, pages = {235 -- 242}, language = {en} } @inproceedings{KoalUlbrichtVierhaus, author = {Koal, Tobias and Ulbricht, Markus and Vierhaus, Heinrich Theodor}, title = {Combining On-Line Fault Detection and Logic Self Repair}, series = {IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS 2012), Tallin, Estonia, 18 - 20 April 2012}, booktitle = {IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits \& Systems (DDECS 2012), Tallin, Estonia, 18 - 20 April 2012}, editor = {Raik, Jaan}, publisher = {IEEE}, address = {Piscataway, NJ}, isbn = {978-1-4673-1185-4}, pages = {288 -- 293}, language = {en} } @inproceedings{KoalUlbrichtEngelkeetal., author = {Koal, Tobias and Ulbricht, Markus and Engelke, Piet and Vierhaus, Heinrich Theodor}, title = {Kombinierte On-Line-Fehlerkompensation und Selbstreparatur f{\"u}r Logik-Baugruppen}, series = {Testmethoden und Zuverl{\"a}ssigkeit von Schaltungen und Systemen, 25. GI/GMM/ITG-Workshop, 24. bis 26. Februar 2013, Dresden}, booktitle = {Testmethoden und Zuverl{\"a}ssigkeit von Schaltungen und Systemen, 25. GI/GMM/ITG-Workshop, 24. bis 26. Februar 2013, Dresden}, publisher = {Fraunhofer-Institut}, address = {Dresden}, language = {de} } @misc{MishurovaSydowThiedeetal., author = {Mishurova, Tatjana and Sydow, Benjamin and Thiede, Tobias and Sizova, Irina and Ulbricht, Alexander and Bambach, Markus and Bruno, Giovanni}, title = {Residual Stress and Microstructure of a Ti-6Al-4V Wire Arc Additive Manufacturing Hybrid Demonstrator}, series = {Metals}, volume = {6}, journal = {Metals}, number = {10}, issn = {2075-4701}, doi = {10.3390/met10060701}, language = {en} } @misc{WenBaroniPerezetal., author = {Wen, Jianan and Baroni, Andrea and P{\´e}rez, Eduardo and Ulbricht, Markus and Wenger, Christian and Krstic, Milos}, title = {Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages}, series = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, journal = {2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, isbn = {978-1-6654-5938-9}, issn = {2765-933X}, doi = {10.1109/DFT56152.2022.9962345}, pages = {1 -- 6}, abstract = {RRAM technology is a promising candidate for implementing efficient AI accelerators with extensive multiply-accumulate operations. By scaling RRAM devices to the synaptic crossbar array, the computations can be realized in situ, avoiding frequent weights transfer between the processing units and memory. Besides, as the computations are conducted in the analog domain with high flexibility, applying multilevel input voltages to the RRAM devices with multilevel conductance states enhances the computational efficiency further. However, several non-idealities existing in emerging RRAM technology may degrade the reliability of the system. In this paper, we measured and investigated the impact of read disturb on RRAM devices with different input voltages, which incurs conductance drifts and introduces errors. The measured data are deployed to simulate the RRAM based AI inference engines with multilevel states.}, language = {en} } @misc{PerezBoschQuesadaMahadevaiahRizzietal., author = {Perez-Bosch Quesada, Emilio and Mahadevaiah, Mamathamba Kalishettyhalli and Rizzi, Tommaso and Wen, Jianan and Ulbricht, Markus and Krstic, Milos and Wenger, Christian and P{\´e}rez, Eduardo}, title = {Experimental Assessment of Multilevel RRAM-based Vector-Matrix Multiplication Operations for In-Memory Computing}, series = {IEEE Transactions on Electron Devices}, volume = {70}, journal = {IEEE Transactions on Electron Devices}, number = {4}, issn = {0018-9383}, doi = {10.1109/TED.2023.3244509}, pages = {2009 -- 2014}, abstract = {Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8x8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices' nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.}, language = {en} }