@misc{FritscherSinghRizzietal., author = {Fritscher, Markus and Singh, Simranjeet and Rizzi, Tommaso and Baroni, Andrea and Reiser, Daniel and Mallah, Maen and Hartmann, David and Bende, Ankit and Kempen, Tim and Uhlmann, Max and Kahmen, Gerhard and Fey, Dietmar and Rana, Vikas and Menzel, Stephan and Reichenbach, Marc and Krstic, Milos and Merchant, Farhad and Wenger, Christian}, title = {A flexible and fast digital twin for RRAM systems applied for training resilient neural networks}, series = {Scientific Reports}, volume = {14}, journal = {Scientific Reports}, number = {1}, publisher = {Springer Science and Business Media LLC}, issn = {2045-2322}, doi = {10.1038/s41598-024-73439-z}, pages = {13}, abstract = {Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the "ideal memristor" which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a "push button" modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).}, language = {en} } @misc{VishwakarmaFritscherHagelaueretal., author = {Vishwakarma, Abhinav and Fritscher, Markus and Hagelauer, Amelie and Reichenbach, Marc}, title = {An RRAM-based building block for reprogrammable non-uniform sampling ADCs}, series = {Information Technology : it}, volume = {65}, journal = {Information Technology : it}, number = {1-2}, issn = {2196-7032}, doi = {10.1515/itit-2023-0021}, pages = {39 -- 51}, language = {en} } @misc{WenVargasZhuetal., author = {Wen, Jianan and Vargas, Fabian Luis and Zhu, Fukun and Reiser, Daniel and Baroni, Andrea and Fritscher, Markus and Perez, Eduardo and Reichenbach, Marc and Wenger, Christian and Krstic, Milos}, title = {RRAMulator : an efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation}, series = {Microelectronics Reliability}, volume = {168}, journal = {Microelectronics Reliability}, publisher = {Elsevier BV}, address = {Amsterdam}, issn = {0026-2714}, doi = {10.1016/j.microrel.2025.115630}, pages = {1 -- 10}, abstract = {The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current-voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector-matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments.}, language = {en} } @misc{SpetzlerFritscherParketal., author = {Spetzler, Benjamin and Fritscher, Markus and Park, Seongae and Kim, Nayoun and Wenger, Christian and Ziegler, Martin}, title = {AI-driven model for optimized pulse programming of memristive devices}, series = {APL Machine Learning}, volume = {3}, journal = {APL Machine Learning}, number = {2}, publisher = {AIP Publishing}, issn = {2770-9019}, doi = {10.1063/5.0251113}, pages = {1 -- 7}, abstract = {Next-generation artificial intelligence (AI) hardware based on memristive devices offers a promising approach to reducing the increasingly large energy consumption of AI applications. However, programming memristive AI hardware to achieve a desired synaptic weight configuration remains challenging because it requires accurate and energy-efficient algorithms for selecting the optimal weight-update pulses. Here, we present a computationally efficient AI model for predicting the weight update of memristive devices and guiding device programming. The synaptic weight-update behavior of bilayer HfO2/TiO2 memristive devices is characterized over a range of pulse parameters to provide experimental data for the AI model. Three different artificial neural network (ANN) configurations are trained and evaluated regarding the amount of training data required for accurate predictions and the computational costs. Finally, we apply the model to an antipulse weight-update process to demonstrate its performance. The results show that accurate and computationally inexpensive predictions are possible with comparatively few datasets and small ANNs. The normalized weight-update processes are predicted with accuracies comparable with larger model architectures but require only 896 floating point operations and 8.33 nJ per inference. This makes the model a promising candidate for integration into AI-driven device controllers as a precise and energy-efficient solution for memristive device programming.}, language = {en} } @misc{FritscherUhlmannOstrovskyyetal., author = {Fritscher, Markus and Uhlmann, Max and Ostrovskyy, Philip and Reiser, Daniel and Chen, Junchao and Wen, Jianan and Schulze, Carsten and Kahmen, Gerhard and Fey, Dietmar and Reichenbach, Marc and Krstic, Milos and Wenger, Christian}, title = {RISC-V CPU design using RRAM-CMOS standard cells}, series = {IEEE transactions on very large scale integration (VLSI) systems}, journal = {IEEE transactions on very large scale integration (VLSI) systems}, editor = {Wenger, Christian}, publisher = {Institute of Electrical and Electronics Engineers (IEEE)}, address = {New York}, issn = {1063-8210}, doi = {10.1109/TVLSI.2025.3554476}, pages = {1 -- 9}, abstract = {The breakdown of Dennard scaling has been the driver for many innovations such as multicore CPUs and has fueled the research into novel devices such as resistive random access memory (RRAM). These devices might be a means to extend the scalability of integrated circuits since they allow for fast and nonvolatile operation. Unfortunately, large analog circuits need to be designed and integrated in order to benefit from these cells, hindering the implementation of large systems. This work elaborates on a novel solution, namely, creating digital standard cells utilizing RRAM devices. Albeit this approach can be used both for small gates and large macroblocks, we illustrate it for a 2T2R-cell. Since RRAM devices can be vertically stacked with transistors, this enables us to construct a nand standard cell, which merely consumes the area of two transistors. This leads to a 25\% area reduction compared to an equivalent CMOS nand gate. We illustrate achievable area savings with a half-adder circuit and integrate this novel cell into a digital standard cell library. A synthesized RISC-V core using RRAM-based cells results in a 10.7\% smaller area than the equivalent design using standard CMOS gates.}, language = {en} }